Lithography Limited Yield Analysis

Clark Beck

doi:10.1117/12.947759

23 July 1985 Lithography Limited Yield Analysis

Clark Beck

Proceedings Volume 0538, Optical Microlithography IV; (1985) https://doi.org/10.1117/12.947759
Event: 1985 Microlithography Conferences, 1985, Santa Clara, United States

Abstract

A computer program has been developed for calculating statistical layout design rules for integrated circuits. The program also calculates the sampling plan required to verify the confidence levels of alignment and circuit element dimensions at develop inspection. The inherent speed and computational accuracy of the computer offers the user a choice of confidence levels depending upon circuit configuration and critical alignments in the process. Finally, the program calculates overall circuit yields as a function of lithography limited margin violations.

Citation Download Citation

Clark Beck "Lithography Limited Yield Analysis", Proc. SPIE 0538, Optical Microlithography IV, (23 July 1985); https://doi.org/10.1117/12.947759

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