Digital Beamforming Radar VLSI Processor

J. Peter Costello

doi:10.1117/12.949705

4 January 1986 Digital Beamforming Radar VLSI Processor

J. Peter Costello

Proceedings Volume 0564, Real-Time Signal Processing VIII; (1986) https://doi.org/10.1117/12.949705
Event: 29th Annual Technical Symposium, 1985, San Diego, United States

Abstract

A radar digital beamformer VLSI architecture is defined which provides the very high-throughput data flow in a modular failure-tolerant structure. A number of VHSIC/VLSI chip implementation approaches were evaluated and tradeoff curves are presented here. The results indicate affordability of radar elemental beamformers including large two-dimensional arrays.

Citation Download Citation

J. Peter Costello "Digital Beamforming Radar VLSI Processor", Proc. SPIE 0564, Real-Time Signal Processing VIII, (4 January 1986); https://doi.org/10.1117/12.949705

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