A Circuit For Evaluating 64Kbit/S Encoding Procedures

J. C. Candy; R. L. Schmidt; H. M. Hang; E. G. Bowen; R. C. Brainard; B. G. Haskell

doi:10.1117/12.969064

25 October 1988 A Circuit For Evaluating 64Kbit/S Encoding Procedures

J. C. Candy, R. L. Schmidt, H. M. Hang, E. G. Bowen, R. C. Brainard, B. G. Haskell

Proceedings Volume 1001, Visual Communications and Image Processing '88: Third in a Series; (1988) https://doi.org/10.1117/12.969064
Event: Visual Communications and Image Processing III, 1988, Cambridge, MA, United States

Abstract

A prototype encoder-decoder that incorporates special VLSI circuits has been set up to demonstrate various interframe encoding techniques in real time. A Video processing chip converts the signal from R-G-B to Y-U-V format and then filters the signal both horizontally and vertically before subsampling it in various ways. A memory control chip reforms the raster into a sequence of 8*8 blocks, at 15 fields per second. A predictor chip derives frame-to-frame difference signals for each block in every other field and interpolates the remaining fields from the predicted ones. Both prediction and interpolation error signals can be encoded using block encoding techniques in a digital signal processor, or by quantizing their DCTs that are generated in a special orthogonal-transform chip. Equivalent inverse processing is available at the receiver. The system is controlled by general purpose microcomputers, one at the transmitter and one at the receiver. The circuit provides a means for evaluating various block encoding techniques and serves as a base for finding suitable subcircuits that can be integrated.

Citation Download Citation

J. C. Candy, R. L. Schmidt, H. M. Hang, E. G. Bowen, R. C. Brainard, and B. G. Haskell "A Circuit For Evaluating 64Kbit/S Encoding Procedures", Proc. SPIE 1001, Visual Communications and Image Processing '88: Third in a Series, (25 October 1988); https://doi.org/10.1117/12.969064

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