A complete set of spintronic hardware building blocks for low power, small footprint, high performance neuromorphic architectures

Samiran Ganguly; Kerem Y. Camsari; Yunfei Gu; Mircea R. Stan; Avik W. Ghosh

doi:10.1117/12.2529697

16 September 2019 A complete set of spintronic hardware building blocks for low power, small footprint, high performance neuromorphic architectures

Samiran Ganguly, Kerem Y. Camsari, Yunfei Gu, Mircea R. Stan, Avik W. Ghosh

Author Affiliations +

Proceedings Volume 11090, Spintronics XII; 110903J (2019) https://doi.org/10.1117/12.2529697
Event: SPIE Nanoscience + Engineering, 2019, San Diego, California, United States

Abstract

The end of Moore’s Law and the rise of “smart” consumer electronics has wide opened the gate for creative hardware design for the next few decades. While linear algebra accelerators and emulated hardware on FPGA has made some advances in this direction, a fundamentally diﬀerent approach is required for reaching the eﬃciency and performance that will be necessary to embed cognitive computing in-situ in these next generation devices. To address this problem, in this work, we present a collection of spintronic hardware building blocks, fabricable with present day technology, that can be used to build biologically inspired neuromorphic hardware. These hardware units provide neuromorphic behavior derived from their physics and manifested in their electrical characteristics, therefore opening the pathway for compact, low power and VLSI grade scalability using these units. The collection contains two types of stochastic neuron (SN) devices: Analog (ASN) and Binary (BSN) as well as multi-level programmable synaptic connections that can be used for implementing compact dendrites. We discuss the area and power savings brought on by these building blocks and compared with an example design using FPGAs. This functionally complete but minimal set of neuromorphic building blocks can be used to implement a variety of neuromorphic architectures, as demonstrated in this work. We end the discussion with design ideas for neuromorphic architectures, which do not merely implement fast linear algebra but go beyond to elevate compact, physics-based field programmable neuromorphic arrays as first class citizens in every designers toolkit.

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Samiran Ganguly, Kerem Y. Camsari, Yunfei Gu, Mircea R. Stan, and Avik W. Ghosh "A complete set of spintronic hardware building blocks for low power, small footprint, high performance neuromorphic architectures", Proc. SPIE 11090, Spintronics XII, 110903J (16 September 2019); https://doi.org/10.1117/12.2529697

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