Presentation + Paper
28 April 2023 DTCO of sequential and monolithic CFET SRAM
Hsiao-Hsuan Liu, Shairfe M. Salahuddin, Boon Teik Chan, Pieter Schuddinck, Yang Xiang, Pieter Weckx, Geert Hellings, Francky Catthoor
Author Affiliations +
Abstract
Sequential and monolithic complementary FET (CFET) have become the most attractive device options for continuing the area scaling of SRAM beyond 5-Å-compatible technology (A5). The stacked architecture of CFET has eradicated the need for PMOS and NMOS (PN) separation and thereby enables cell height scaling of 40% compared to 10-Å-compatible technology (A10) forksheet (FS) SRAM. However, the routing becomes challenging with aggressive area scaling. This work proposes interconnect designs for A5 CFET SRAM and explores process integration options for corresponding solutions.
Conference Presentation
© (2023) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Hsiao-Hsuan Liu, Shairfe M. Salahuddin, Boon Teik Chan, Pieter Schuddinck, Yang Xiang, Pieter Weckx, Geert Hellings, and Francky Catthoor "DTCO of sequential and monolithic CFET SRAM", Proc. SPIE 12495, DTCO and Computational Patterning II, 124950Z (28 April 2023); https://doi.org/10.1117/12.2657524
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KEYWORDS
Fin field effect transistors

Back end of line

Silicon

Design rules

Metals

Epitaxy

Fabrication

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