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In modern digital integrated-circuit designs, standard-cell libraries are key foundations. The increased leakage current, complicated design rules, and restrictive layout space make the task of designing standard cells meeting both electrical characteristic requirements and layout constraints a significant challenge. Transistor sizing can help determine an optimal set of transistor sizes of the standard-cell circuit under specified design constraints and desired circuit optimization goals. In this work, as a refinement of the existing approaches, a new method is proposed to find suitable initial values and reduce the electric characteristics deviation. Preliminary results indicate that the proposed method can be effective in 20-nm-grade standard-cell optimization.
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