Design and verification of a kind of ECC IP core with prolongable bit width

Yiqian Luo; Junshuai Li; Xu Jiang

doi:10.1117/12.3004999

25 September 2023 Design and verification of a kind of ECC IP core with prolongable bit width

Yiqian Luo, Junshuai Li, Xu Jiang

Proceedings Volume 12788, Second International Conference on Energy, Power, and Electrical Technology (ICEPET 2023); 127881G (2023) https://doi.org/10.1117/12.3004999
Event: Second International Conference on Energy, Power, and Electrical Technology (ICEPET 2023), 2023, Kuala Lumpur, Malaysia

Abstract

Nowadays, with the rapid development of automotive electronics, ECC, as a functional safety mechanism with high reliability, has become increasingly important in the design of automotive chips. Based on the Hsiao code and parallel algorithm, the Verilog HDL is adopted to design the ECC IP core supporting the data coding and decoding within 247bit, and the verification platform is established based on the UVM for functional verification. The verification results show that the ECC IP core can achieve the error correction of data 1bit and error detection of over 2bit, and can expand the coding bit width to achieve multi-scene reuse. The functional coverage ratio and code coverage ratio reach 100%.

(2023) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Yiqian Luo, Junshuai Li, and Xu Jiang "Design and verification of a kind of ECC IP core with prolongable bit width", Proc. SPIE 12788, Second International Conference on Energy, Power, and Electrical Technology (ICEPET 2023), 127881G (25 September 2023); https://doi.org/10.1117/12.3004999

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