Investigation of latch-up phenomenon in sea-of-gate ASIC devices

Tam T. Le; D. Mainz; R. Torres; J. Kinney; B. Glenn; Hoang Huy Hoang

doi:10.1117/12.156527

15 September 1993 Investigation of latch-up phenomenon in sea-of-gate ASIC devices

Tam T. Le, D. Mainz, R. Torres, J. Kinney, B. Glenn, Hoang Huy Hoang

Proceedings Volume 2090, Multilevel Interconnection: Issues That Impact Competitiveness; (1993) https://doi.org/10.1117/12.156527
Event: Microelectronic Processing '93, 1993, Monterey, CA, United States

Abstract

As the VLSI/ULSI device density is increasing common failure mechanisms, such as internal latch-up phenomenon in sea-of-gate ASIC devices, are surfacing and becoming an important reliability issue. The traditional latch-up phenomenon sensitivity assessment techniques are no longer adequate; because the phenomenon is not limited to causes externally induced at the device peripherals but in process-induced defects as well. Therefore, an understanding of this effect is critical to both manufacturing and engineering communities. The purpose of this paper is to report a study of latch-ups in sea-of-gate (continuous arrays) ASIC devices. Two techniques, traditional and laser-induced testings, are presented.

Citation Download Citation

Tam T. Le, D. Mainz, R. Torres, J. Kinney, B. Glenn, and Hoang Huy Hoang "Investigation of latch-up phenomenon in sea-of-gate ASIC devices", Proc. SPIE 2090, Multilevel Interconnection: Issues That Impact Competitiveness, (15 September 1993); https://doi.org/10.1117/12.156527

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