Real-time implementation of JPEG encoder/decoder

Thomas M. Czyszczon; Roy S. Czernikowski; Muhammad E. Shaaban; Kenneth W. Hsu

doi:10.1117/12.311097

18 June 1998 Real-time implementation of JPEG encoder/decoder

Thomas M. Czyszczon, Roy S. Czernikowski, Muhammad E. Shaaban, Kenneth W. Hsu

Proceedings Volume 3422, Input/Output and Imaging Technologies; (1998) https://doi.org/10.1117/12.311097
Event: Asia Pacific Symposium on Optoelectronics '98, 1998, Taipei, Taiwan

Abstract

With the immense size of images, compression has become a common way of minimizing the amount of storage necessary for images. This is also beneficial for transmission purposes. The Joint Photographic Experts Group (JPEG) standard is frequently used for still images. This standard is very flexible and many of the same algorithms can be used for video applications. Video applications require large amounts of data to be processed every second. Therefore, the following describes the hardware design of a chip allowing for high-speed compression. The design uses the JPEG algorithms and is targeted towards ASIC design. Further plans include use of field programmable gate arrays (FPGAs). The hardware design is based on grayscale images and only works with the raw image data.

Citation Download Citation

Thomas M. Czyszczon, Roy S. Czernikowski, Muhammad E. Shaaban, and Kenneth W. Hsu "Real-time implementation of JPEG encoder/decoder", Proc. SPIE 3422, Input/Output and Imaging Technologies, (18 June 1998); https://doi.org/10.1117/12.311097

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