Paper
7 December 2001 Efficient VLSI implementation of bit plane coder of JPEG 2000
Kishore Andra, Tinku Acharya, Chaitali Chakrabarti
Author Affiliations +
Abstract
To overcome many drawbacks in the current JPEG standard for still image compression, a new standard, JPEG2000, is under development by the International Standard Organization. Embedded bit plane coding is the heart of the JPEG2000 encoder. This encoder is more complex and has significantly higher computational requirements compared to the entropy encoding in current JPEG standard. Because of the inherent bit-wise processing of the entropy encoder in JPEG2000, memory traffic is a substantial component in software implementation. However, in hardware implementation, the lookup tables can be mapped to logic gates and memory accesses for the state bit computation can be reduced significantly by careful design. In this paper, we present an efficient VLSI architecture for embedded bit-plane coding in JPEG2000 that reduces the number of memory accesses. To better understand the interaction of this architecture with the rest of the coder, we also present a system level architecture for efficient implementation of JPEG2000 in hardware.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kishore Andra, Tinku Acharya, and Chaitali Chakrabarti "Efficient VLSI implementation of bit plane coder of JPEG 2000", Proc. SPIE 4472, Applications of Digital Image Processing XXIV, (7 December 2001); https://doi.org/10.1117/12.449757
Lens.org Logo
CITATIONS
Cited by 20 scholarly publications.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
JPEG2000

Discrete wavelet transforms

Computer programming

Microelectromechanical systems

Image compression

Surface plasmons

Multiplexers

RELATED CONTENT


Back to Top