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20 September 2001 Design and simulation of reusable IP for image convolution algorithm
Jiannong N. Tong, Xuecheng Zou, Xubang Shen
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Proceedings Volume 4552, Image Matching and Analysis; (2001) https://doi.org/10.1117/12.441504
Event: Multispectral Image Processing and Pattern Recognition, 2001, Wuhan, China
Abstract
This paper proposes an IP hierarchy based on 3 X 3 convolution template to construct large-scale image convolution architecture, such as 6 X 6, 9 X 9 or more. It's an aid to speed up the designing for image- processing hardware system. The key hierarchies of 3 X 3 image convolution consist of parallel convolutions and pipelined multipliers. The hierarchies are designed for top- model with structural VHDL and all sub-models with RTL VHDL. The system is divided into some models and connected all after synthesized independently. Cadence and Synopsys are utilized for VHDL simulation and for synthesis respectively in order to obtain the preferable effects.
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Jiannong N. Tong, Xuecheng Zou, and Xubang Shen "Design and simulation of reusable IP for image convolution algorithm", Proc. SPIE 4552, Image Matching and Analysis, (20 September 2001); https://doi.org/10.1117/12.441504
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KEYWORDS
Convolution
Computer simulations
Image analysis
Image processing
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