Capacitive MEMS sensors exhibit an excellent noise performance, high sensitivity and low power consumption. They offer a huge range of applications, being the accelerometer one of its main uses. In this work, we present the design of a capacitance-to-voltage converter in CMOS technology to measure the acceleration from the capacitance variations. It is based on a low-power, fully-differential transimpedance amplifier with low input impedance and a very low input noise.
This work presents a new continuous-time equalization approach to overcome the limited bandwidth of integrated CMOS photodetectors. It is based on a split-path topology that features completely decoupled controls for boosting and gain; this capability allows a better tuning of the equalizer in comparison with other architectures based on the degenerated differential pair, which is particularly helpful to achieve a proper calibration of the system. The equalizer is intended to enhance the bandwidth of CMOS standard n-well/p-bulk differential photodiodes (DPDs), which falls below 10MHz representing a bottleneck in fully integrated optoelectronic interfaces to fulfill the low-cost requirements of modern smart sensors. The proposed equalizer has been simulated in a 65nm CMOS process and biased with a single supply voltage of 1V, where the bandwidth of the DPD has been increased up to 3 GHz.
We present a low-voltage merged CDR and cntinuous-time adaptive equalizer capable to compensate the attenu- ation of a SI-POF channel while at the same time synchronizing and regenerating the incoming signal in a single stage. The system operates at 1.25 Gbps for NRZ modulation through a 50-m SI-POF channel and it is designed in standard 0.18-μm CMOS fed at 1 V with a power consumption of 43.4 mW.
KEYWORDS: Virtual colonoscopy, Signal attenuation, Linear filtering, Digital filtering, Signal detection, Phase only filters, Capacitors, Polymer optical fibers, Telecommunications, Analog electronics
A multi-rate low-voltage continuous-time adaptive equalizer is presented in this paper. It was designed to compensate the high-frequency attenuation of a 50-m 1-mm core step-index plastic optical fiber (SI-POF) for input data ranges from 400 Mbps up to 1.25 Gbps. The equalization is based on the power-spectrum technique and the circuit operates with a single supply voltage of 1 V. The structure is formed by two loops which do not interact with each other; one loop adapts to changes in the channel length and the other in the data rates.
KEYWORDS: Modulation, Receivers, Signal processing, Prototyping, Phase only filters, Amplifiers, Data communications, Polymer optical fibers, Telecommunications, Signal to noise ratio
This paper presents a front-end for short-reach high-speed optical communications that compensates the limited bandwidth of 1-mm 50-m step-index plastic optical fiber (SI-POF). For that purpose, it combines two techniques: continuous-time equalization and duobinary modulation. An addition of both enables the receiver to operate at 3.125 Gbps. The prototype contains a transimpedance amplifier, a continuous-time equalizer and a duobinary decoder. The prototype has been implemented in a cost-effective 0.18-μm CMOS process and is fed with 1.8 V.
KEYWORDS: Phase only filters, Telecommunications, Transistors, Analog electronics, Resistance, Monte Carlo methods, Prototyping, Navigation systems, Virtual colonoscopy, Device simulation
We present a new CMOS analog continuous-time equalizer that overcomes the limitations of the most widely used continuous-time equalizer, the degenerated differential pair. The equalizer has been proved for multi-gigabit short-range applications targeting up to 2 Gb/s through a 50-m SI-POF. The prototype consumes 2.7 mW for a 1-V supply voltage.
KEYWORDS: Phase only filters, Virtual colonoscopy, Transistors, Linear filtering, CMOS technology, Electronic filtering, Signal attenuation, Control systems, Modulation, Eye
A new low-voltage high-speed CMOS fully-differential adaptive equalizer based on the spectrum-balancing technique is presented. It was designed to compensate the strong attenuation of the transmitted signal through a 50-m length SI-POF. The proposed equalizer, which targets a 2.5 Gb/s transmission for a simple NRZ modulation, was designed in a standard 0.18-μm CMOS process and uses a 1-V supply voltage with a total power consumption below 17.3 mW. An enhancement in the signal BW from 100 MHz to 1.8 GHz for a 50-m POF length is achieved.
KEYWORDS: Amplifiers, Sensors, Analog electronics, Linear filtering, Signal processing, Transistors, CMOS technology, Interference (communication), Sensor networks, Signal detection
This paper presents a simple 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated lock-in amplifiers. The proposed OpAmp has been designed in a standard 0.18 μm CMOS technology. For a 1.2 V single supply and 68.6 μW power consumption, simulations shows a 81 dB open loop gain, 64° phase margin, 13 MHz unity gain frequency for a capacitive load of 10pF and 75 dB CMRR. Adaptive biasing provides 30.7 V/μs slew-rate for a 10 pF load. A compact and reliable lock-in amplifier (LIA) has been designed using the proposed circuit. The designed LIA has a power consumption of 135 μW and recovers signals up to 1 MHz with relative errors below 2.6 % for noise and interference signals of the same amplitude as the signal of interest.
KEYWORDS: Linear filtering, Optical filters, Phase only filters, Bandpass filters, Digital filtering, Analog electronics, Modulation, Electronic filtering, Data communications, Telecommunications
In modern high-speed data communications systems, the limited bandwidth of the channel results in inter-symbol interference (ISI) at the received signal, which has to be compensated by equalization. Typically, equalization at the receiver is preferred to equalization at the emitter because it can be designed to take into account the varying characteristics of the channel in what is called adaptive equalization. Continuous-time adaptive equalizers base their operation on the fact that the spectrum of the incoming signal is known prior to its reception, so the degradation caused by the channel can be evaluated and subsequently corrected by comparing the power measured at different frequency ranges with the value expected in theory. In this paper, an ideal pseudo-random NRZ signal will be used, whose power spectrum can be described by a squared sinc function. Four different architectures have been proposed in the literature to carry out power spectrum comparison: two band-pass filters; one high-pass and one low-pass filter; one all-pass and one low-pass filter; and two low-pass filters. This work analyzes the differences between these techniques on the operation of continuous-time adaptive equalizers, establishing filter design criteria based on the characteristics of the channel and the equalizer filter. The paper is organized as follows: Section I is the introduction; Section 2 gives and overview of the spectrum balancing technique architectures; Section 3 outlines the proposed criteria to set the filter bandwidth; finally, conclusions are drawn in Section 4.
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