In this paper, we propose methodologies used in a software system for checking process friendliness (including lithography friendliness) and routability (including pin accessibility) of standard cells. In the process of designing physical layouts of standard cells, it is essential to consider their process friendliness since specific cells have very high tendencies to create process weakpoints (which include lithography hotspots) after their instances are placed and routed. On the other hand, at advanced process nodes, the routability of standard cells must also be considered since there are combined trends of increasing pin densities and increasing design rule complexities. Experimental results show that our software system is able to effectively detect problematic standard cells which have critical process friendliness and/or routability issues.
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