This work presents a new continuous-time equalization approach to overcome the limited bandwidth of integrated CMOS photodetectors. It is based on a split-path topology that features completely decoupled controls for boosting and gain; this capability allows a better tuning of the equalizer in comparison with other architectures based on the degenerated differential pair, which is particularly helpful to achieve a proper calibration of the system. The equalizer is intended to enhance the bandwidth of CMOS standard n-well/p-bulk differential photodiodes (DPDs), which falls below 10MHz representing a bottleneck in fully integrated optoelectronic interfaces to fulfill the low-cost requirements of modern smart sensors. The proposed equalizer has been simulated in a 65nm CMOS process and biased with a single supply voltage of 1V, where the bandwidth of the DPD has been increased up to 3 GHz.
KEYWORDS: Virtual colonoscopy, Signal attenuation, Linear filtering, Digital filtering, Signal detection, Phase only filters, Capacitors, Polymer optical fibers, Telecommunications, Analog electronics
A multi-rate low-voltage continuous-time adaptive equalizer is presented in this paper. It was designed to compensate the high-frequency attenuation of a 50-m 1-mm core step-index plastic optical fiber (SI-POF) for input data ranges from 400 Mbps up to 1.25 Gbps. The equalization is based on the power-spectrum technique and the circuit operates with a single supply voltage of 1 V. The structure is formed by two loops which do not interact with each other; one loop adapts to changes in the channel length and the other in the data rates.
KEYWORDS: Modulation, Receivers, Signal processing, Prototyping, Phase only filters, Amplifiers, Data communications, Polymer optical fibers, Telecommunications, Signal to noise ratio
This paper presents a front-end for short-reach high-speed optical communications that compensates the limited bandwidth of 1-mm 50-m step-index plastic optical fiber (SI-POF). For that purpose, it combines two techniques: continuous-time equalization and duobinary modulation. An addition of both enables the receiver to operate at 3.125 Gbps. The prototype contains a transimpedance amplifier, a continuous-time equalizer and a duobinary decoder. The prototype has been implemented in a cost-effective 0.18-μm CMOS process and is fed with 1.8 V.
KEYWORDS: Phase only filters, Telecommunications, Transistors, Analog electronics, Resistance, Monte Carlo methods, Prototyping, Navigation systems, Virtual colonoscopy, Device simulation
We present a new CMOS analog continuous-time equalizer that overcomes the limitations of the most widely used continuous-time equalizer, the degenerated differential pair. The equalizer has been proved for multi-gigabit short-range applications targeting up to 2 Gb/s through a 50-m SI-POF. The prototype consumes 2.7 mW for a 1-V supply voltage.
KEYWORDS: Phase only filters, Virtual colonoscopy, Transistors, Linear filtering, CMOS technology, Electronic filtering, Signal attenuation, Control systems, Modulation, Eye
A new low-voltage high-speed CMOS fully-differential adaptive equalizer based on the spectrum-balancing technique is presented. It was designed to compensate the strong attenuation of the transmitted signal through a 50-m length SI-POF. The proposed equalizer, which targets a 2.5 Gb/s transmission for a simple NRZ modulation, was designed in a standard 0.18-μm CMOS process and uses a 1-V supply voltage with a total power consumption below 17.3 mW. An enhancement in the signal BW from 100 MHz to 1.8 GHz for a 50-m POF length is achieved.
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