In the paper, methods for designing fast processing algorithms for Xilinx FPGA are presented. The paper describes different algorithm design methods on FPGA (iterative, pipelined, loop unrolled). The given methods' characteristics (potential performance, efficiency, and resource usage) are presented and compared. Algorithm design on FPGA using High-Level Synthesis technique (which allows using high-level languages C and C++) and hardware description language (HDL) are compared. The effect of the High-Level Synthesis technique on the performance of implemented algorithms, resource usage, and design time is described. This paper presents an experiment (based on checksum "Fletcher-16") that investigates the advantages of the HLS technique and the HDL.
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