3D-NAND manufacturers are racing to increase the storage capacity by increasing the number of stacked layers. As the increase of the number of stacked layers, complex process, films stress and deep-etch tilting effects were observed to affect the device overlay control significantly. Traditional optical overlay metrology via scribe-lane image based overlay (IBO) has its constraint to entirely reflecting in-device overlay behavior because of the differences on pattern density, film stack and stress to memory array. In this study, Patterned Wafer Geometry (PWG) tool was adopted to collect wafer shape step-by-step. The in-plane deviation (IPD) and Gen4 overlay derived from wafer shape was used as efficient indexes to distinguish which metrology is representative of indevice overlay for critical layers. High voltage scanning electron microscope (HV-SEM) and optical scatterometry critical dimension measurement (SCD) were adopted separately combining with traditional scribe-lane IBO metrology for in-device overlay improvement through applying non-zero offset (NZO) overlay compensation at different photo layers.
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