An experimental technique for quantitatively characterizing edge effect contributions in transmission through thick
photomasks is described and evaluated through electromagnetic simulation. The technique consists of comparing the 0th
order transmission for various duty cycles to the expected experimental behavior from a thin mask model. The real
electric field component from the edges is proportional to the shift in the position of the minimum energy in the 0th order
field away from the expected thin mask location. The square root of the minimum 0th order diffraction energy
normalized to a clear mask gives the imaginary edge contribution. The results indicate that Alternating Phase Shifting
Masks (ALT-PSM) and Attenuating Phase Shifting Masks (ATT-PSM) technologies have significant edge effects on the
order of 0.1λ to 0.2λ per edge respectively, as well as polarization dependence. For periods of 2 wavelengths and larger
these edge contribution values are nearly independent of pitch. The existence of an imaginary (or quadrature) phase
component is shown to result in an additive linear variation of line edge shortening through focus. This tilt can be
interpreted as a focus shift of the normal parabolic behavior and is about 0.5 Rayleigh units (RU). This focus shift
depends to some extent on the surrounding layout as well as the feature itself.
Exploratory prototype DfM tools, methodologies and emerging physical process models are described. The examples
include new platforms for collaboration on process/device/circuits, visualization and quantification of manufacturing
effects at the mask layout level, and advances toward fast-CAD models for lithography, CMP, etch and photomasks. The
examples have evolved from research supported over the last several years by DARPA, SRC, Industry and the Sate of
California U.C. Discovery Program. DfM tools must enable complexity management with very fast first-cut accurate
models across process, device and circuit performance with new modes of collaboration. Collaborations can be promoted
by supporting simultaneous views in naturally intuitive parameters for each contributor. An important theme is to shift
the view point of the statistical variation in timing and power upstream from gate level CD distributions to a more
deterministic set of sources of variations in characterized processes. Many of these nonidealities of manufacturing can be
expressed at the mask plane in terms of lateral impact functions to capture effects not included in design rules. Pattern
Matching and Perturbation Formulations are shown to be well suited for quantifying these sources of variation.
As a consequence of the reduction in the pixel sizes of charge coupled device (CCD) image sensors, the sensitivity of these
sensors has decreased, which means that their signal-to-noise ratio (SNR) has also decreased even though the amount of noise
is kept constant. In order to maintain and even increase the SNR, we evaluated a simulation method for estimating the
sensitivity and smear noise. Smear noise and sensitivity are defined by the number of electrons in vertical registers and
photodiodes, respectively. We used a finite-difference time-domain (FDTD) method to simulate the light energy which is
proportional to electrons generated in a Si substrate. Using this simulation, we were able to estimate sensitivity and smear noise
accurately and optimize the structure of on-chip lenses (OCLs) with respect to these parameters. When we optimized an OCL
structure for an interline transfer (IT)-CCD having 1.86-&mgr;m-square pixels, we found that the optimal thickness of the OCL in
regards to the smear noise was 0.25 &mgr;m thinner than the optimal thickness for the sensitivity. This result demonstrates that
when designing the structures of image sensors, including the OCL shape, it is not only necessary to consider the sensitivity,
but it is also important to take the smear noise into consideration.
We found that accurate estimation of the actual resist patterns and impurity profiles is the key point in the case of image sensors below 2.5 um square cell size. We apply a resist patterning process model to our process/device simulation. In the photolithography process simulation, each patterned resist layer exhibits own resist corner rounding regarding as differences such as resist thickness and wavelength of stepper. For the ion implant processes and thermal processes, channeling and doped impurity diffusion models are newly applied. We introduced two dimensional Monte Carlo simulation in order to estimate channelings affected by impurity species, accelerating voltage of implanter and crystallographic orientation. This enables to get impurity profiles of implant processes with mega order accelerating energy. Three dimensional impurity diffusion profiles can be obtained by using the optimized ratio of lateral diffusion to perpendicular diffusion. We have confirmed the advantage of the new simulation method by evaluation of device characteristics in small size CCDs.
An alternative phase shift mask (alt-PSM) is a promising device for extending optical lithography to finer design rules. There have been few reports, however, on the mask's ability to identify phase defects. We report here an alt-PSM of a dual-trench type for KrF exposure, with programmed quartz defects used to evaluate defect printability by measuring aerial images with a Zeiss MSM100 measuring system. The experimental results are simulated using the TEMPEST program. First, a critical comparison of the simulation and the experiment is conducted. The actual measured topography of quartz defects are used in the simulation. Moreover, a general simulation study on defect printability using an alt-PSM for ArF exposure is conducted. The defect dimensions, which produce critical CD errors are determined by simulation that takes into account the full 3-dimensional structure of phase defects as well as a simplified structure. The critical dimensions of an isolated defect identified by the alt-PSM of a single-trench type for ArF exposure are 240 nm in bottom diameter and 50 degrees in height (phase) for the cylindrical shape and 240 nm in bottom diameter and 90 degrees in height (phase) for the rotating trapezoidal shape, where the CD error limit is +/- 5%.
In this paper, we propose a new analysis method to quantify the performance of optical proximity effect correction (OPC) as well as the gauge capability of in-process quality control (IPQC) monitors. The method consists of two stages. The first stage is to quantify the gauge capability of IPQC monitor patters for representing 'across chip line width variation' (ACLV). The second one is to verify OPC by using the IPQC monitor patterns as verified in the first stage. Our new analysis method has bene found to be remarkably effective and quite useful to optimize OPC parameters and other methods in attempting to reduce ACLV, the most critical factor in producing high-end logic devices with a design rule of 0.15 micrometers and below.
For a lithography process with a design rule of 0.18 micrometers and beyond, the most critical issue is the gate critical dimension (CD) control because it affects the circuit performance especially for high-end logic devices directly. The gate CD variation is generally categorized into two folds. The first one is CD variation affected by optical and process proximity effects, which is pattern layout dependent errors and can be treated by automatic optical proximity effect correction (OPC). The second one is across chip line width variation (ACLV) caused by aberration of stepper/scanner exposure tools and mask writing error. Although both two have been studied in detail respectively, the composite errors are not studied sufficiently. This is because these errors can not necessarily be quantified for all the pattern layout configuration exists in the actual device chips. In this paper we will propose a new analysis method to quantify OPC performance and gauge capability of in-process quality control (IPQC) monitors. The method consists of two parts. The first is to verify validity of OPC by using IPQC monitor patterns and the second is to quantify gauge capability of the IPQC monitor patterns for representing ACLV. Our new analysis method is significantly effective and persuasive for verifying OPC performance as well as gauge capability of IPQC monitor patterns. It is also quite useful to optimize OPC parameters and methods to reduce ACLV that is most critical to obtain high-end logic devices with a design rule of 0.15 um and below.
A new method to optimize the structure of an alternative phase shifting mask (alt-PSM) with dual trench type has been developed form the viewpoint of pattern placement error as well as conventional factors of light intensity contrast and exposure-defocus window (ED-window). By using this, the pattern placement error caused by either the phase error or defocus has been reduced. By the simulation, the optimum structure for reducing the pattern placement error is with a phase difference of about 170 degree(s) between phase shifted and non-shifted area. The pattern placement error for 0.13 micrometers lines and spaces can be reduced to less than 2.5 nm from -0.3 to 0.3 micrometers defocus by this optimum. A high contrast and a large ED-window can be obtained as well. However, high accuracy of mask fabrication technique is required. In the experiment, we have evaluated line and space patterns for a 0.13 micrometers node logic gate design rule. It showed less than 7.5 nm errors in the required DOF for the mask with the optimized mask structure.
For the fine patterning of gate layers on embedded DRAM is logic devices with a design rule of 0.13 micrometers and below, we have optimized the double exposure technique with an alternative phase shifting mask using KrF excimer laser exposure. Based on the study over lithography process latitude with respect to exposure-defocus window, overlay margin and mask fabrication feasibility, we have adopted a process as that patterns in logic circuits are delineated by the combination of alt-PSM and a trim mask made of Cr shielding patterns on an attenuated phase shifting mask, while patterns in DRAM cells are delineated by the latter att-PSM exposure only. With considering a mask error enhancement factor, optical condition and optical proximity effect correction for the alt-PSM and trim mask are also optimized, then, 0.13 micrometers embedded DRAM in logic patterns have been fabricated with a sufficient common lithography process window by the KrF excimer laser exposure.
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