Proceedings Article | 28 April 2023
KEYWORDS: Design and modelling, Field programmable gate arrays, Logic, Mathematical optimization, Computer simulations, Algorithm development, Parallel computing, Information security, Data storage, Clocks
In recent years, with the rapid development of network information technology, problems related to information security have also emerged, such as the leakage of personal privacy information, and the monitoring or tampering of important information. These problems affect social order all the time, and even threaten national security seriously. Cipher is a common method to solve information security problems. Ballet series block cipher algorithm is a lightweight cipher algorithm using Lai-Massey and ARX structure. Aiming at the Ballet-128/128 algorithm, Verilog HDL is used to implement the algorithm in FPGA, and two design schemes are proposed. Firstly, a scheme is proposed to complete the key expansion module first, and then perform 46 rounds of encryption/decryption iterative calculation on the algorithm. This scheme adopts the method of Finite State Machine to effectively reduce resource consumption. Secondly, on this basis, the encryption/decryption operation process of the algorithm adopts a 46-stage Pipeline structure design, which can realize the encryption/decryption operation of multiple groups of data, and further improve the operation efficiency of the algorithm. Finally, in the Quartus II 13.0.1 environment, the Cyclone III series EP3C40F780C6 chip is used for engineering implementation. The engineering implementation results of the two design methods are consistent with the standard vector, and the operating efficiency is effectively improved. In the end, the throughput rate of the Finite State Machine design of the algorithm is 0.45Gbps, and the throughput rate of the Pipeline structure design optimized on this basis can reach 24.75Gbps, which can quickly encrypt/decrypt a large amount of data, satisfying most of the encryption/decryption systems.
