In FinFET transistors, the parasitic capacitance between the source/drain contact and the metal gate tends to be high, and this can negatively impact device performance. Adding a metal gate recess step can reduce capacitance, but unfortunately it also increases the metal gate resistance. By changing the metal gate recess profile, a good balance between resistance and capacitance can be achieved to reduce RC. In this work, we investigate FinFET metal gate recess profile settings and how changes in profile settings affect FinFET resistance and parasitic capacitance (R and C). Metal gate recess dimensional changes and profile changes can modify parasitic capacitance and impact electrical performance. We performed a virtual DOE where we varied the gate CD, recess depths, and metal gate recess profiles to understand the impact of these changes on FinFET resistance, capacitance, and electrical performance. Different recess profiles, such as sharp head and antenna shapes, were simulated using SEMulator3D® virtual process fabrication and pattern dependence modeling. Subsequent electrical analysis was performed to extract resistance and capacitance values and to model device transistor behavior. We replicated the process to calculate the resistance and capacitance for a GAAFET, and investigated performance trends during changes in gate CD, tungsten (W) etchback and recess profile variations.
Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development is a major contributor to time and cost overruns. The growing inability to characterize many of the subtle and complicated features and yield limiting factors of a given technology is another serious constraint. We demonstrate the use of process modeling, virtual wafer fabrication, and virtual metrology in process development of advanced logic and memory. Accurate and predictive process modeling, in combination with virtual metrology enables the characterization of any feature on any given structure, is becoming a key requirement in advanced technology development. Virtual fabrication also accelerates the semiconductor development cycle, by substituting limited and lengthy wafer-based experiments with fast, large-scale virtual design of experiment. Several applications of virtual process modeling and metrology are illustrated in 3D NAND, DRAM, and logic technology. These applications include studies of 3D NAND pillar etch alignment (including tilt, twist, and bowing), DRAM capacitor process window optimization, advanced FinFET logic pitch-walking, and BEOL performance optimization.
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