As 193-nm immersion lithography will likely be required to be extended beyond 40-nm half-pitch, multiple patterning lithography will become a necessity in that scenario. We present a cost-effective approach for double patterning with extendibility to sub-10-nm half-pitch division, which is a very promising candidate for advanced logic nodes. Spacers on sufficiently sloped sidewalls directly transferred from a low-contrast photoresist profile can be removed by anisotropic etching. Alternatively, spacer gaps for defining trenches may be prevented from penetrating to the substrate by the use of sloped sidewalls. These sloped sidewalls are defined by attenuated phase-shift mask features, which impart phase shifts other than 180 deg or 0 deg. Loop trimming and sidewall spacer definition are accomplished in a single photomask. In addition, there is now an extra ability to define random, arbitrary breaks in the spacer-defined pattern, without using an extra exposure for specified cuts. In this way, a single exposure using a modified attenuated phase-shift photomask, followed by a low-contrast development process around the sensitivity limit, is sufficient to pattern regularly arranged spacer-defined lines at fixed pitch while including some predetermined line cut locations.
Publisher’s Note: This paper, originally published on 4/12/2013, was replaced with a corrected/revised version on
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As 193 nm immersion lithography may be required to be extended beyond 20 nm node, multiple patterning lithography will become a necessity in that scenario. We present a cost-effective approach for 22 nm half-pitch double patterning, with extendibility to sub-10 nm half-pitch pitch division. Spacers on sufficiently sloped sidewalls directly transferred from a low-contrast photoresist profile can be removed by anisotropic etching. Alternatively, spacer gaps for defining trenches may be prevented from penetrating to the substrate by the use of sloped sidewalls. These sloped sidewalls are defined by attenuated phase shift mask (attPSM) features which impart phase shifts other than 180 or 0 degrees. Such features can be accommodated in the process flow for fabricating phase shift masks by the definition of one or two extra layers of processing in the mask shop. Aerial image simulations show this photomask design is more effective in generating sloped foot profiles in the photoresist than simply using sub-resolution features or reducing the width of the clear region. Loop trimming and sidewall spacer definition are accomplished in a single photomask. In addition, there is now an extra ability to define random, arbitrary breaks in the spacer-defined pattern, without using an extra exposure for specified cuts. In this way, a single exposure of a low-contrast photoresist around the sensitivity limit using a modified attenuated phase-shift photomask is sufficient to pattern regularly arranged spacer-defined lines at fixed pitch with irregularly arranged breaks, or 'cuts' in the lines.
New non-volatile memory, like RRAM, needs high aspect ratio (AR) bi-layer resist (BLR) pillar pattern to act as etch mask for sub-50 nm cell metal pillar definition [1]. HSQ/AR3 resist pillar is still not enough for patterning RRAM pillar since (1) AR is limited at ~7 which is still marginal in etching resistance, (2) BLR resist pillar CD is limited by dry development positive CD-bias, (3) BLR resist pillar is easy to collapse during venting to air, and (4) BLR resist pillar AR is lower for looser pillar densities which degrades the etching resistance. Tone reverse process flow for forming RRAM pillar is developed in this study to overcome these drawbacks. Thermal reflow assists the formation of sub-30 nm contact holes (C/Hs) on ZEP520A e-beam resist. Experimental results are summarized below. All the resolved CDs of C/H on ZEP520A with designed CD (DCD) of 40-100 nm are larger than 100 nm without proximity effect correction (PEC) on blank RRAM film stacking substrate. Smallest etched C/H on LTO after thermal reflow process is 14.4 nm. CD-bias of etched C/H on LTO relative to that of resist C/H after thermal reflow is larger for looser C/Hs. Thermal reflow of ZEP520A is C/H size before reflow, density, sidewall profile and reflow time dependent. NiOx hard mask is apparently without deposited into C/H smaller than 20 nm due to PVD deposition limit since the NiOx dot image disappeared after etching of LTO film for tone reverse. Smallest CD of TiN/Ti/HfOx RRAM pillar by tone reverse process flow is 28.8 nm using NiOx hard mask dot CD of 22.9 nm formed on 20.5 nm etched C/H on LTO after reflow. Uniform CD distribution of designed C/Hs result in uniformly distributed CDs after reflow / LTO etching / RRAM pillar formation. In summary, tone reverse process flow for RRAM pillar formation is successfully developed which has potential for patterning RRAM pillar of CD smaller than 20 nm in the help of NiOx hard mask deposition by atomic layer deposition (ALD) into oxide C/H in the future.
New applications on memory and logic devices need to form line shape pattern below 20 nm. Most of the prior articles for studying HSQ line CD resolution applied hot or cold (non-room temperature (RT)) development, salty development, KOH-based development or high concentration TMAH developer (like 25%) to push CD resolution to below 10 nm but these methods are not standard IC process compatible with 2.38% TMAH development at RT. E-beam lithography processes are applied to investigate CD resolution on RRAM film stacking of TiN/Ti/HfOx with or without proximity effect correction (PEC). Both dose and shape (line CD and pitch) modulations are applied in this study to obtain finest line width resolution using IC process compatible 2.38% TMAH developer at RT. Experimental results are summarized below. Lowest base dose of HSQ for pattern to be resolvable is larger than 1,000 (μC/cm2). Smallest line CD of 13.1 nm for designed CD of 5 nm (G4) is resolved to 2 separate lines on R1st dense-line pattern with e-beam dose of 5,000 (μC/cm2) assisted by dose PEC. Two lines of R1st dense-pattern is merged to single line of 14.7 nm at 10,000 (μC/cm2). 2lines dense-line pattern is clearly resolved to 2 separate lines at 1,500 (μC/cm2) but merged to one line at 2,000 (μC/cm2). Iso-line on the right of two dense-lines of 2lines pattern contributes backscattered dose which increases the line width. 5lines dense-line pattern could only resolve to 18.3 nm. Iso-line R1st_1L is resolvable to 18.5 nm with uniform distribution of CD across the line and 13.6 nm is also resolved with more rough line edge. In summary, sub-14 nm line width of HSQ could be resolved by the combination of e-beam dose and shape modulations using standard 2.38% TAMH developer. This process is suitable for applications using metal oxide films.
High AR bi-layer resist (BLR) pillar with organic underlayer (UL) is inevitable for etching of thick RRAM film
stacking considering etch selectivity to avoid collapse. Selection of UL is a key factor to determine the AR of
BLR pillar and selectivity during etching of hard mask (HM) and RRAM film stacking. In this work, e-beam
patterning of HSQ pillar under various e-beam dose conditions, pattern density and HSQ thicknesses are studied
on carbon highly contained UL TBLC-100PM. Hard mask layer of low temperature nitride (LTN) or oxide (LTO)
above TiN/Ti/HfOx RRAM film stacking are also studied for achieving highest HSQ CD resolution by reducing
e-beam proximity effect. Fogging effect is studied with various e-beam dose of the L/S=1/20 isolated pillar array
which is far from the other arrays of 36 μm.
Experimental results are summarized below. Etch rates (etch resistance) of TBLC-100PM UL under fluorine or
chlorine-based plasmas are lower (higher) than that of AR3-600 UL with low carbon contained. Thicker LTN
HM is necessary for higher HSQ pillar CD resolution. HSQ pillar CD resolution on LTO HM is higher than that
on LTN HM. Smallest CD of HSQ pillar is 23.1 nm. Fogging effect is strong for TBLC-100PM where e-beam
dose could affect the shape of HSQ pillar of neighboring array. This is not observed for AR3-600 UL. HSQ pillar
CD resolution is highest for HSQ coated at 2000 rpm. Small change of HSQ coating speed could degrade CD
resolution and imaging contrast drastically which may come from the fogging effect.
The optimized dry development condition of low-k etcher obtained before is transferred to and optimized in
DPSII metal etcher in this study to avoid resist pillar collapse, etch residual magnification, process continuity
and tool simplicity. Three key process parameters of oxygen flow rate, bottom power and e-chuck temperature
are studied for vertical pillars with various pattern densities. HSQ pillar patterning is transferred from diluted
Fox-12 to commercialized XR1541-002 where the film thickness and patterned CD are matched. LTN hard
mask (HM) of 100 nm thick above RRAM film stack is deposited for reducing proximity effect of
XR1541-002 and improving etch resistance.
Experimental results are summarized below. Highest AR of ~3.9 for HSQ/AR3 BLR semi-dense L/S=1/3
pillar with vertical profile is obtained with optimized dry develop condition of O2, N2, flow rates, chamber
pressure and temperature, top and bottom power of 8, 5, sccm, 3 mTorr, 80oC, 200 and 100 watts respectively.
AR is lower for looser pattern density. Oxygen flow rate and bottom power are the most critical process
parameters for obtaining high AR BLR pillar and most vertical profile of pillar, just like the case of low-k
etcher. E-chuck temperature is critical in profile control. Etch residual is magnified to broaden LTN pillar CD
and degrade CD uniformity (CDU) if its etch process is not immediately continued after dry development
process.
Multiple patterning is the only known way to extend current 193 nm immersion-based optical lithography beyond
40 nm half-pitch. A highly effective technique for multiple patterning uses self-aligned etched spacers to define the
tightest pitch lines as critical features. However, to complete the patterning, the lines must be cut with at least one
separate additional exposure. In order to reduce the costs associated with multiple cut locations, it is proposed to group
the locations into portions of larger features. Specifically, the cut locations can be the intersection of the spacer lines and
the overlap of at least two polygons of opposite exposure polarity. The cost reduction is determined by the reduced
number of exposures, as well as the looser pitch and dimensions of the exposures. Besides cost reduction, greater
immunity to exposure shot noise (if EUV or EBL is used for cutting) is provided by the use of larger polygons. The
benefits of complementary polarity patterning based on these key issues will be analyzed for the 10 nm half-pitch
application, and extensions to even smaller half-pitches will be discussed.
E-beam exposed HSQ resist pillar (island) is commonly used as the hard mask for dry etching. However, HSQ
pillar is prone to collapse without any substrate pre-treatment. CD resolution of HSQ pattern also depends on the
aging effect. In this work, factors of (1) designed CD (DCD) (2) dose vs L/S ratio (3) beam current (4)
underlayer (UL) (5) post-coat-delay (PCD) time before e-beam writing are studied for forming stable and
reproducible sub-22 nm HSQ pillar. Three kinds of underlayer are evaluated, i.e. AR3-600, ZEP520A and
TDUR-N700.
Experimental results are summarized below. A wider dose window of forming sub-22 nm HSQ pillar with looser
L/S ratio or smaller designed CD is obtained. CD variation for all pattern density conditions is due to the
proximity effect from beam blur. AR3-600 is shown to be the most suitable UL for HSQ pillar. CD of HSQ pillar
increases with thicker AR3-600 layer. PCD range for stable CDs of HSQ pillar with DCD of 20 nm is larger than
that with 15 nm.
RRAM is the candidate of next generation new non-volatile memory. The etched stacking film thickness of
RRAM cell pillar is not easy to reduce below 50 nm during CD scaling down since part of RRAM cell pillar
height is removed during CMP polishing of dielectric passivation to expose the pillar top surface for the
following metallization process. Therefore resist pillar pattern with high aspect ratio (AR) is needed to act as
etch mask for defining thick RRAM cell pillar structure. Bilayer resist (BLR) process is most suitable for
forming high AR pattern. Dry develop process is the key step for generating sub-32 nm high AR BLR pillar
pattern. In this study optimization of dry develop process is investigated for high AR pillar with hydrogen
silsesquioxane (HSQ) as upper thin imaging layer for e-beam exposure and AR3-600 as the thick underlayer
for etching resistant.
Experimental results are summarized below. Highest AR of ~6 for HSQ/AR3 BLR semi-dense L/S=1/2 pillar
with vertical profile is obtained under optimized dry develop condition with O2, N2, Ar flow rates, chamber
pressure, top and bottom power of 8, 5, 0 sccm, 1 mTorr, 200 and 100 watts respectively. AR is lower for
looser pattern density. CD variation between HSQ/AR3-600 BLR pillars with different pattern density is
optimized to 5.6 nm. The pillar profile is vertical in vacuum for pattern of any density but distorts more severe
for denser pattern during ventilation to atmosphere. The most critical process parameters for obtaining high
aspect ratio BLR pillar are O2 flow rate and top power. Sidewall profile angle of pillar is mainly dependent on
chamber pressure and bottom power.
20 nm contact hole (C/H) patterning is applicable for sub-22 nm technology node applications. Dependence of C/H
CD window on critical process parameters is important for process stability and repeatability. Post applied baking
(PAB) condition, resist thickness, develop time, and dry etch rate are considered to be the most important process
parameters for e-beam chain scission resist ZEP520A C/H patterning. In this paper, PAB temperatures (TPAB) are
investigated at temperatures between lower than glass transition temperature (TG) and much higher than TF. Effects of these process parameters on 20 nm +/-10% C/H CD window for various pattern densities and e-beam doses are
studied. The critical process parameters are determined by their effects on CD window size, C/H sidewall profile,
proximity effect immunity, ΔCD/ΔDose slope, and etch selectivity.
Experimental results are summarized below. Thinnest ZEP520A film has the largest 20nm +/-10% CD window on
D-D plot for various L/S ratios and doses. The dosage window of smaller C/H CD is larger. The proximity effect is
negligible for 50 nm ZEP520A baked at 200°C/300 sec. No apparent effect is found in CD window on D-D plot for develop time as short as 30 sec. PAB condition is most critical than the other process parameters in determining resist density and polymerization which affect e-beam scattering and chain scission in resist film and therefore affects CD resolution and window. PAB condition of 140°C/60 sec is most desirable in terms of CD window on D-D plot, C/H sidewall profile, dry etch rate and proximity effect.
HSQ island formed by directly e-beam exposure (DE) and wet development is used as a dry etching mask material.
However, the HSQ islands with high aspect ratio are susceptible to collapse during wet development process due to
surface tension. To improve this, HSQ-rod and HSQ-Tip structures were achieved by dry stripping of ZEP520A
after thermal reflow of ultra-thin HSQ (hydrogen silsesquioxane) gap-filled (GF) ZEP520A contact holes (C/H) in
previous study. Aspect ratio of HSQ island formed by latter process is higher than that by the former since the latter
is without wet develop procedure which tends to washout the HSQ island. In this paper, gap-fill processes followed
by a hardening process to prevent bending of HSQ island are studied to form sub-50 nm HSQ islands (rod or tip)
with high aspect ratio. Diluted HSQ is used to gap-fill the exposed ZEP520A C/H or C/H after thermal reflow. The
hardening processes include high temperature baking and e-beam curing with high beam current.
Experimental results are summarized below. Aspect ratio of GF type HSQ-rod larger than 7 is obtained. Bending of
GF type HSQ island (rod or tip) with high aspect ratio is also observed. HSQ-rod hardened by high temperature
baking tends to fracture. E-beam curing proves to be efficient for HSQ island (rod or tip) hardening and the required curing doses are dependent on HSQ-rod CD. Smallest HSQ-Tip CD hardened by e-beam curing is ~12.5nm. It is found that e-beam curing of GF type HSQ island and e-beam exposure of DE type HSQ island has the same effect and mechanism in cross-linking of HSQ molecules to increase mechanical strength.
In previous study HSQ air-tip high density array with sub-20 nm radius of curvature were obtained by stripping
ZEP520A after thermal reflow of ultra-thin HSQ (hydrogen silsesquioxane) gap-filled ZEP520A contact holes
(C/H). And, the mechanical strength of HSQ spacer to resist shrinkage and thermal reflow of ZEP520A was found
to play a dual role on the deformation of HSQ-coated C/H and thus the formation of HSQ air-tip. In this paper,
effects of HSQ spacer width and thermal reflow of ZEP520A for HSQ air-tip formation are further studied for
optimal process window. The effects of pattern and process parameters on the HSQ spacer width and shrink rate of
thermal reflow are also evaluated. In short, thicker HSQ spacer is obtained for smaller C/H array size, looser pattern
density, larger C/H CD, lower HSQ dilution ratio and thinner resist thickness. Dependence of HSQ spacer width on
HSQ dilution ratio is stronger for thicker ZEP520A which implies that HSQ is deficient to fill the sidewall for
deeper C/H. Lower shrink rate of diluted HSQ-coated ZEP520A under reflow is obtained for smaller C/H array size,
looser pattern density, larger C/H CD, lower HSQ dilution ratio and thinner resist thickness. All of these
relationships reflect the dependence of thermal reflow on the resistant effect of HSQ spacer width. Optimal process
and pattern conditions for determining critical HSQ spacer width to form HSQ air-tip without bending or HSQ
air-rod without shrunk of hole are described in detail.
KEYWORDS: Deep ultraviolet, Photoresist processing, Critical dimension metrology, Cadmium, Chromium, Electron beams, Electron beam lithography, Solids, Electron beam direct write lithography, Lithography
Electron beam direct writing (EBDW) resist process is slow in throughput but has the highest linewidth resolution
among all the lithography techniques. However the e-beam energy is high enough to cut off the polymer chain of
DUV chemically amplified resist (CAR) and thus in this paper, DUV-assisted e-beam resist process is studied to
increase throughput. The C/H critical dimension (CD) with e-beam exposure only increases for larger dose. E-beam
dose-to-size of C/H is found to be independent on pattern density. The smallest CD resolved is 30.2 nm for 30 nm
designed CD. DUV pre-exposed resist resolves the same C/H CD size with lower e-beam dose. Largest e-beam
dose reduction with DUV-assistance is ~40% for 50 and 70 nm designed CD of C/Hs. BARC coating and multiple
DUV pre-exposures with variable depths are studied for obtaining a vertical profile like that exposed by e-beam
only.
Hydrogen silsesquioxane (HSQ) bilayer resist (BLR) processes are attractive to obtain nano-sized features with high aspect ratio by dry-transferring thin e-beam pattern to thick underlayer to strengthen the etch resistance. However, there are drawbacks of high e-beam dosage for HSQ patterning and difficulty in controlling the underlayer resist profile by O2 plasma with anisotropic etching. In this study gap-fill type HSQ/ZEP520A BLR processes were studied to overcome these problems. The advantage of gap-fill type BLR processes is that the dosage for patterning on thick ZEP520A e-beam positive resist is not as high as that for HSQ and the resist profile can be tuned by exposure and development processes without depending on O2 plasma. By gap-filling of HSQ in ZEP520A trench patterns and then stripping ZEP520A by O2 plasma the tone is conversed from trench to line. The gap filling quality attributes include (1) the void size and number of HSQ lines and (2) spacer adhesion on HSQ line edge. Only the non-diluted HSQ solution could completely fill the trench and the HSQ line formed after stripping of ZEP520A. The spacer formed by diluted HSQ is found to be composed of oxide without any ZEP520A-related elements by FTIR analysis. The ZEP520A trench CD monotonically increases with decrease of W/L ratio. The HSQ line CD also follows the same trend. The extension of HSQ in ZEP520A, i.e. HSQ line CD minus ZEP520A trench CD, basically follows the reverse trend. It is therefore concluded that extension of HSQ lines in ZEP520A and HSQ spacers are formed from the diffused HSQ in trench sidewall without any reaction with ZEP520A. Voids were generally observed at the bottom of the HSQ line. Size and quantity of voids are larger for lower W/L ratios, indicating that the voids were formed due to insufficient HSQ volume for gap-filling. Increasing e-beam dose, baking or reflow temperature, and reflow of ZEP520A before HSQ coating could reduce the void formation. Multiple gap-filling with 1:14 diluted HSQ can lead to void-free lines. The HSQ spacer becomes thicker with less diluted HSQ, slower spin speed, reduced ZEP520A development time and HSQ PCB temperature. The smallest HSQ island of 46.3 nm was obtained by two reflows plus HSQ gap filling and baking processes, a significant size for the hardmask of metal island etching or mold of contact-hole nano-imprint for 45 nm node. The width of HSQ spacers is generally within 10-25 nm, potentially applicable to transistor gate patterning in 22 nm node and beyond.
The CD shrinkage by thermal reflow technique was frequently used for the formation of contact hole (C/H) of fine size. However, such technique is seldom used for line (trench)/space type patterns with complicate layout, like 6T-SRAM pattern. One of the reasons is the shape distortion of the designed layout after thermal reflow which results in the difficulty in CD control. In this study ultra-thin hydrogen silsesquioxane (HSQ)-coated ZEP520A trenchs are used to investigate the CD shrinkage effect and integrity of the shape after thermal reflow. 6T-SRAM transistor gate with various width/length (W/L) ratios is used as the test pattern. HSQ diluted by methyl-isobutyl ketone (MIBK) with 1:3 and 1:14 volume ratios was coated on ZEP520A trenchs. Post-applied baking (PAB) conditions of non-HSQ coated ZEP520A are split to find the optimal CD uniformity. The effects of thickness of HSQ, dilution ratio, spin speed of HSQ on the CD and shape after thermal reflow at various temperatures for HSQ-coated ZEP520A trench patterns are also studied. Multiple thermal reflows at 160oC-180oC are applied to obtain the best shrinkage results. It is found that the non-HSQ coated ZEP520A trench with all W/L ratios shrunk at 160oC. The smallest shrunk trench of 33.6 nm top-CD with 1/50 W/L ratio is obtained for HSQ (1:14)-coated ZEP520A for two thermal reflows at 160 oC/90 sec while 35.8 nm top-CD of the same W/L ratio is obtained after one 180oC/90sec reflow. Both sizes could meet the CD requirement of 32nm node and beyond. Above all, the HSQ-coated ZEP520A keeps the shape of trench pattern after one or multiple thermal reflows.
E-beam chain scission resist ZEP520A with 400 nm thickness was studied for sub-10 nm contact holes with high
aspect ratio formed by CD shrinkage techniques of thermal reflow and SAFIER. CD shrinkage temperatures and
repeating times were process parameters to be studied. Design parameters of initial CD of 40-100 nm and
line/space ratio of contact hole with 1/3 and >1/20 before shrinkage were also studied. Process window of
thermal reflow for the aforementioned initial CDs is 155-165 °C while that of SAFIER is 150-165 °C. There is
no shrinkage for both methods for temperatures below 140 °C. CD shrinkage rates of both methods decrease for
more than one time of heating. Thermal reflow has a larger CD shrinkage rate than SAFIER. The dependence of
shrinkage rate on initial CD size and spatial frequency is not apparent. CD nearly ceases shrinking for further
heatings as the CD reaches an ultimate CD size. The ultimate CD for a larger initial CD is also larger. The
smallest shrunk CD is found to be 5.8 nm with aspect ratio over sixty for 50 nm initial designed CD. CD
uniformity also studied for both processes with 3-sigma smaller than +/-10%. The contact holes shrunk by
thermal reflow process generally show funnel-shape profiles while those shrunk by SAFIER process show
similar profiles with wider undercut. In summary, the thermal reflow process results in better profile while the
SAFIER with slower CD shrinkage rate has a better control on CD and uniformity.
ZEP520A e-beam processes for 40-100nm contact holes were studied for application of phase change memory (PCM) device prototyping. Resist baking, e-beam and development process parameters were investigated on the isolated and semi-dense (1:3) contact holes. PAB temperature for minimum exposure dose-to-size (ESIZE) is 70°C. ESIZE of 200°C PAB is 250 μC/cm2 while that of 70°C is 120 μC/cm2 for 100nm contact hole. ESIZE of contact hole increases very quickly as the CD gets smaller than 60nm. CDs with beam currents of 100pA and 200pA are nearly the same while that with 2nA differs much. Sidewall profiles of contact holes exposed by 100pA and 200pA are near 90° while that exposed with 2nA is tapered. ESIZE decreases with development time. Bottom of contact hole is broadened for prolonged development time. CDs after PDB are not changed. There is little difference in CD between isolated and semi-dense patterns. CD uniformity on the corner and center of contact-hole array are around 5% (+/-3σ), showing a very weak proximity effect. Inter-layer mix-and-match processes were applied to PCM manufacturing. Cross-shaped alignment marks results in the strongest signal waveform on TiW bottom electrode than oxide and TiN/Ti. Mix-and-match PCM device structure was, for the first time, ever demonstrated.
The rising demand for processing small charges of ASICs, FPGAs or optolectronic devices at reduced costs promotes the application of e-beam direct-write lithography. This technology requires automated tools which integrate the overall processing sequence: coating, baking, developing, wet etching, stripping and cleaning. These tools should also enable clustering with e-beam writers and dry etchers for seamless processing. The novel integrated STEAG HamaTech ModuTrack track system enables automated processing of a batch of single substrates like wafers or photomasks, while for each substrate different processing methods and sequences may be chosen. The processing modules may also be operated individually. This integrated tool concept is demonstrated referring to the recently installed 8" wafer and 6" photomask ModuTrack at ITRI (Industrial Technology Research Institute of Taiwan), where the process development for wafer e-beam direct-write (EBDW) lithography and photomask processing is ongoing. The processing modules deliver outstanding capabilities, like coating resist with 50nm thickness within a total range of 1% uniformity, and developing 45nm resist dense lines both uniform and repeatable.
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