In the past few decades, leading edge logic technology scaling has been the main driver for semiconductor metrology developments. As traditional device scaling is slowing down, the semiconductor industry is focusing also on heterogeneous integration approaches, which leverage advanced packaging technologies to integrate devices designed and manufactured separately using the most suitable process technology for each device. Heterogeneous integration presents significant metrology challenges, which are different from what is encountered at the logic device level in terms of materials and specifically dimensions. Large-scale 3D structures need to be characterized with unprecedented accuracies and advanced optical techniques play a pivotal role. In this paper, some metrology challenges in heterogeneous integration are introduced and discussed related to TSV characterization including depth and reveal height, wafer bonding measurements, and dimensional and overlay metrology for processing leading to bump receivers and bump formation. Current capabilities utilizing various imaging and interferometry techniques are presented and their limitations discussed.

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Katherine Sieg, Christopher Bottoms, Christopher J. Waskiewicz, Alejandro Matos Mejia, Junwon Han, Shahid Butt, Daniel Schmidt, Stefan Schoeche, Alexander Hamer, and Alex Hubbard, "Large feature wafer level in-line optical metrology techniques for advanced packaging schemes," Proc. SPIE 12955, Metrology, Inspection, and Process Control XXXVIII, 129551P (Presented at SPIE Advanced Lithography + Patterning: February 29, 2024; Published: 16 April 2024); https://doi.org/10.1117/12.3012149.