The current scale of online video streaming requires hardware accelerated video transcoding solutions. Historically, hardware solutions have been excellent at offloading the computationally intensive tasks from CPUs, but often came with the penalty of being inflexible and not quickly adaptable to emerging market trends. We are presenting an architecture, which maintains all the benefits of hardware acceleration but also adds an unparalleled level of programmability and flexibility. This architecture supports a wide spectrum of markets ranging from ultra-low latency encoding all the way to high quality video on demand (VOD) markets with only firmware changes. These capabilities are achieved by a strategic combination of built-in hardware acceleration components and many embedded CPUs that have full control over the video encoding pipeline flow. This architecture not only provides deterministic timing, which is critical for ultra-low latency transcoding, but it also offers flexibility and programmability allowing robust product roadmaps through simple firmware updates.

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Pavel Novotny and Avinash Ramachandran, "Adaptive hardware acceleration architecture for ASIC transcoding," Proc. SPIE 13137, Applications of Digital Image Processing XLVII, 131370U (Presented at Optical Engineering + Applications: August 21, 2024; Published: 30 September 2024); https://doi.org/10.1117/12.3031734.