In this presentation, I'd like to share my perspective on chemistry and, specifically, on chemical safety in the '80s. That perspective, incidentally, will come from my experience managing one of the world's largest industrial health laboratories. I will make some observations about chemical safety in the '80s as they pertain to the photographic industry and, of course, to other industries that utilize photographic technologies and processes.

Sidewall erosion in plasma etching is employed to obtain sub-micron features derived from 1.5 to gum sized features which are printed in a standard scanning UV projector. The smallest features reliably obtained are 0.3μm wide.

A new method for the production of submicron photopatterns is described. Good quality images are obtainable even under very low contrast illumination through the use of photobleachable materials in conjunction with standard photoresists. The method consists of applying a thin photobleachable layer to the photoresist surface prior to the conventional exposure step. The bleachable layer (contrast-enhancing layer or CEL) is subsequently removed and the resist developed in the ordinary way. Examples of vertical-walled submicron patterns fabricated using an Optimetrix 10:1 DSW system demonstrate that the CEL process compares well with other advanced photolithographic techniques.

A review of key developments in the field of inorganic resist systems is presented. We also discuss the role that inorganic resist systems can play in submicron optical lithography for VLSI. Because of a unique set of material characteristics, the optical lithographic performance of these resist systems surpasses that of any known organic resist system, and even exceeds that expected for a resist having infinite contrast. Effects such as edge sharpening and photobleaching compensate for the resolution-limiting diffraction effects in optical lithography. We discuss a two-stage imaging mechanism, consisting of the definition of a thin image layer followed by anisotropic, wet chemical etching to replicate this high resolution image into the entire thickness of the Ge-Se film. The high absorbance of these films to the exposing radiation eliminates problems associated with substrate reflectivity and their resistance to oxygen plasma allows the use of a bi-level scheme that alleviates problems associated with device topography. Sensitivity of this resist system to the entire UV spectrum permits the use of a single resist system for all current and future optical exposure tools.

A manufacturable, high resolution photoresist process is described. This process was developed to increase production margins on the 1.0 μm geometries used in the Hewlett Packard NMOS III process: This was accomplished through a modification of the portable conformal mask (PCM) technique,2 which drastically reduced substrate effects on GCA. wafer stepper performance by the introduction of a bleachable dye in the bottom photoresist layer.

Manual alignment data had been collected for the new Perkin-Elmer M341 in a pilot line operation. The alignment data were measured by using an electrical test structure which was incorporated in an E-beam mask set, together with a product device, to monitor the alignment between two critical mask layers. The results were the actual overall misalignment data on devices which were processed in a typical semiconductor IC fabrication environment. A new analytical method was used to analyze the alignment data to identify the contribution from translation, rotation, expansion, scan, or cross-scan components. The contribution from the E-beam masks was also analyzed.

We describe the procedures and results of overlay performance evaluation conducted on production Micralign Series Model 500s. Studies of machine-to-contact print and machine-to-machine overlay, stability, and automatic alignment are presented. Preliminary results on automatic alignment indicate that the 98% limit of total overlay error - alignment plus distortion - can be kept below 0.3 μm.

Many techniques aimed at reducing the magnitude of overlay error are practiced within the semiconductor industry. For example, attempts are made to manufacture masks as similar to each other as possible, and exposure tools used for successive product levels are selected to be as well-matched as possible. Although these and similar techniques have contributed to some reduction in overlay error, the degree of improvement has not been remarkable for several reasons. For example, there exist some contributing factors which are not easily brought under control, such as wafer-specific effects. Also, different masks interact with different exposure tools through a variety of mechanisms which produce a remarkable diversity of performance results.

This paper describes the comparison of registration accuracies at device fabrication level, and the analysis of their registration errors, in 1/10 steppers(GCA 4800 DSW), 1/1 scanning projection aligns (Perkin-Elmer 140), and their hybrid. The registration accuracy (6R) was evaluated by fabricating an n-MOS test device of double poly-Si structure at 50 - 54 dies a 4"0 wafer. For the analysis of registration errors, five independent factors such as alignment error (6A), machine stability-and-compatibility error (6D), mask error (6M), mask thermal expansion error (6T), and residual error(6r), which are responsible for registration error, were quantitatively measured, including their long period variation.

The characteristic image placement errors of both 1:1 projection aligners and 10:1 reduction wafer steppers are studied with reference to the overlay difference between them. Analytical models have been developed in recent years which allow the user of these sophisticated aligners to mathematically identify the many components of pattern-to-pattern registration errors. Using these models and experimental data, it is shown how the mixing of the two types of exposure tool can be done successfully. For the fabrication of present generation devices, it is possible to mix steppers using global alignment capability with 1:1 projection aligners. A realistic production overlay budget is developed for 10:1 steppers, 1:1 projection aligners, and for a process which mixes the two.

Although wafer stepper technology seems to be the general trend in fabrication of VLSI circuits, the semiconductor industry is still evaluating the relative merits of 1X, 5X and 10X magnification. Field-proven early model reduction steppers are now being challenged by new lower-cost 1:1 steppers with comparable specifications, such as the Canon FPA-112FA. The present study takes a close look at the Canon FPA-112FA 1:1 wafer stepper as a production viable VLSI tool. Results obtained in processing a 2-poly NMOS process (1.7 micron minimum space) are presented.

The historic trend toward smaller working feature size within the semiconductor industry is making increased demands on the exposure tools. More and more, exposure tools are expected to provide lithography at and below the 1 pm level. To meet this requirement the technology of optical instruments must stretch its limits to stave off such competing technologies as Electron Beam and X-ray. The theoretical resolution for an optical system is proportional to the numerical aperture of the projection optics and inversely to the wavelength of the illumination used. Reducing either quantity will lead to increased resolution of the exposing system. The use of exposure tools which are mainly composed of reflecting elements provides the opportunity to utilize short wavelength UV, and thus to gain increased resolution, without redesigning the projection optics system. Simultaneously, the option of designing for high numerical apertures is not precluded by the use of reflective systems. This paper describes how submicron resolution is achievable with currently available projection equipment by a simple filtering of the illumination source and utilizing deep UV resists. Data is provided on resolution, resist profiles, step coverage, and wafer throughput.

Recently, Merck has introduced a new novolak resin based positive resist system with improved performance in VLSI semiconductor processing. Performance data is presented in some detail. Topics stressed include the performance during aluminium etching using chlorine containing plasma and high current ion implantation. It will be shown that excellent performance can be obtained using certain processing techniques when severe thermal/reactive plasma environments are encountered.

Waycoat WX-159 is a positive resist designed for use with optical aligners operating in the mid-UV (280-320 nm). Spectral data is presented indicating potential applications of WX-159 resist in the deep UV (220-280 nm) and near UV (330-400 nm) as well. Data are presented demonstrating the use of WX-159 in conventional UV as well as the mid-UV regime. The resist with both metal containing and metal ion free developers is characterized by two techniques: 1) contrast curve of remaining film thickness after development versus exposure energy, and 2) dissolution rate monitor comparison of exposed and unexposed WX-159 films. The impact of developer composition on resist profile is shown wherein WX-402 developer produces near vertical, flat topped, micron size WX-159 images.

Computer simulation of the photodoping and lateral diffusion of silver during exposure is used to explore the theoretical potential of inorganic resists and to explore the extent to which it is realized in the Ge-Se resist system. The resist exposure is modeled as photodoping, silver into the substrate at the bottom of a bleachable sensitized layer. The silver concentration is assumed to be uniform vertically throughout the layer and allowed to diffuse laterally. The amount of photo-doping is proportional to the product of the intensity of light reaching the bottom of the sensitized layer and the local silver concentration. The layer is assumed to have a bleachable absorption proportional to the silver concentration , a nonbleachable absorption and a bleaching rate coefficient. A FORTRAN algorithm for solving the resulting coupled differential equations has been developed for use with the SAMPLE program. Both dynamic bleaching (hole burning) and lateral diffusion can lead to a sharper edge and/or higher contrast in the photodoped silver concentration than those in the incident exposure aerial image. For the 100A thick Ge-Se system at 0.75 urn features on the GCA DSW4800 stepper, the diffusion length is two times larger than the feature size, so that the contrast is equal to that of the aerial image at any exposure time. For large features with large transition region between the clear and dark fields contrast enhancement can be obtained using thick resists ($>100 A sup 0$) at the expanse of longer exposure time. For Ge-Se the lateral diffusion combined with photodoping saturation allow a feature dependent amplification of the relative silver concentrations for various feature sizes. This together, with the high contrast development process [1] allow inorganic resist to image well at low contrast exposure.

A simple and reliable technique is used to describe the selectivity for removal of exposed and unexposed resist for various developer systems. The technique requires no special apparatus. All that is necessary is a method of exposing photoresist and measuring resist thickness, although the method is simplified if a step and repeat exposure system is used. Measurements of resist thickness are made after resist development over an incremented span of exposures. The logarithm of exposure vs. retained resist thickness curves give excellent prediction of sidewall profiles. A contrast parameter, Y, can be calculated for a particular process giving a figure of merit to compare processing methods. Information concerning developer activity can be extracted from two exposure thresholds; Ei, the induction to removal, and E0, the complete removal of photoresist. Further, this technique pertains not only to develop processing, but to any part of the photoresist process which has an impact on contrast. This paper reports on the use of the technique to characterize and compare two positive resist developers: One that is formulated for high resolution and high contrast (Shipley Microposit MF-314, CD31) and one that is formulated for high throughput and aggressive process performance (Shipley Microposit MF-312, 3:2 dilution). The developers have been evaluated for the three common modes of resist development (immersion, spray, and puddle) and at differing temperatures, spin speeds, nozzle pressures, and with and without a post exposure bake. It is demonstrated that this technique of evaluation delineates significantly between develop systems as regards contrast, provides a firm basis for process optimization aimed at high resolution, and advances understanding of the dynamics of positive resist development.

A discussion of the general parameters used in resist formulation is given. Characterization of the resist and its metal and non-metal developers includes: resist chemistry, coating properties and film thickness control, photospeed at two major wavelengths, contrast parameters, resolution capability, thermal flow properties, dry etch resistance, adhesion and removal characteristics. The new system emphasizes a higher degree of manufacturing control to increase yields in high resolution device manufacturing.

The production of VLSI semiconductor devices requires the patterning of circuits with minimum linewidths under 2 microns. Deep UV lithography utilizing radiation in the 220-280nm regime has the capability of meeting this resolution requirement in a production environment. Conventional photoresists have not adequate resolution and sensitivity in the deep UV. This paper presents data on a negative acting deep UV resist, WX303, which combines good photospeed with high resolution. Recent studies with WX303 imaged on a Micralign 500 operating in the UV-2 mode, demonstrated the submicron capabilities of this resist. Data is also presented on WX303 image profile modification by changes in development time and exposure energy.

A number of multilevel resist processes are being developed to solve the difficult problem of producing submicrometer circuit features over profiled surfaces. The application of a novel illumination system, comprising a microwave powered source and catadioptic optical system, to accomplish the pattern transfer step through planarization resists by deep UV flood exposure is characterized. The microwave powered lamp generates 114 watts of deep UV (200 - 260 nm) with an efficiency of greater than 9%. Data showing an effec-tive bulb lifetime of 500 hours or more is presented. Optical filtering techniques are described which effectively attenuate energy above 245 nm and result in excellent critical dimension control. Enhancing areas of the deep UV spectrum by using microwave powered bulbs with additive materials such as cadmium is discussed, and spectral data presented. Problem areas for successful use of the PCM process in production are defined and solutions are discussed. Finally, extensions of microwave powered deep UV lamp technology to other areas of microlithography are discussed.

The influence of mask defects on integrated circuits yield was studied by comparing the data given by an automatic mask inspection system to the die sort yield at probe test level. It was found that the yield losses due to mask defects can vary from a few % to more than 50 %, as a function of the type of defects, layer involved and defect size.

Simple test structures have been used to evaluate the yield capabilities of a photoengraving process. The structures consist of meander tracks placed between two interdigitating sets of fingers so that electrical tests reveal both the breaks in the track and any shorts between the track and the fingers. This paper illustrates some aspects of the yield obtained with a standard positive resist photoengraving process applied to single-layer metallisation and to polysilicon over a range of feature sizes. Simple mathematical models are employed to convert yield data into fault density data and to conveniently express the dependence on feature size. The models are applicable to both test structures and circuits.

Photomask defects have long been known to be a source of device failure at wafer probe test. Mask inspection coupled with defect repair and mask production process control is the means to reduce the number of photomask defects. Further impact on probe yield with improved photomask quality requires advances in both defect detection sensitivity and defect repair capability. This paper presents a model for considering the impact of increased defect detection sensitivity on wafer probe yield. The model integrates concepts of the frequency distribution of defects by size and the probability of fatal effect of defects. As inspection sensitivity increases and the defects found are eliminated, substantial increases in wafer probe yield can be expected. The model takes into account variables such as design linewidths, device type, critical mask levels, and defect type.

In this paper, we present a mask inspection methodology and procedure that involves direct X-Y measurements. A group of dice is selected for overlay measurement; four measurement targets were laid out in the kerf of each die. The measured coordinates are then fit-ted to either a "historical" grid, which reflects the individual tool bias, or to an ideal grid squares fashion. Measurements are done using a Nikon X-Y laser interferometric measurement system, which provides a reference grid. The stability of the measurement system is essential. We then apply appropriate statistics to the residual after the fit to determine the overlay performance. Statistical methods play an important role in the product disposition. The acceptance criterion is, however, a compromise between the cost for mask making and the final device yield. In order to satisfy the demand on mask houses for quality of masks and high volume, mixing lithographic tools in mask making has become more popular, in particular, mixing optical and E-beam tools. In this paper, we also discuss the inspection procedure for mixing different lithographic tools.

Defect types for chrome photomask blanks are defined. Their probable causes and effects on device yield are explained. Three systems are presented which can detect pinholes, surface defects, or both. Repeatability and detection probability of pinholes and surface defects are demonstrated for the Coberly Plate Inspector 714, which inspects for both types simultaneously. Raw material quality, in defects or pinholes per unit area, is correlated to finished photomask quality as defined by KLA-101 inspection. Through raw material inspection it is possible to predict and improve mask quality and yield.

The continuing growth in the complexity of Integrated Circuits shows no signs of stopping. The industry has developed a series of equipments that have enabled even finer geometry to be economically reproduced onto the wafer. The latest of these, the direct step on wafer systems deliberately sacrifice area of exposure for resolution and accuracy. By projecting single die images that may be individually aligned to the die on the wafer, the stepper systems offered a tool to advance the industry. However these systems put a new strain on the production of reticles. (Fig.1). What had previously been only an intermediate tool for the creation of master masks now became the master in its own right. The Electron Beam Microfabricators provided a tool ideally suited to the creation of near perfect reticles. However, because of the use of the reticle as a direct production tool it is vital to ensure that the reticle is defect free before installing it, and, by checking the exposed pattern on silicon, to confirm that the reticle is still good in the stepper. A single mask defect may only kill a single die, a single reticle defect may kill all dies. In response to this challenge a new series of instruments has emerged to check the single die pattern not against its neighbour which may have been stepped from the same faulty reticle but directly against the CAD data.

This paper describes work done at Contrex on the development and implementation of an automatic in-aligner reticle qualification system called the WaferVision 2000. This system performs reticle inspection for defects by automatic optical inspection of the photoresist patterns on a wafer printed by the reticle. The inspection is done by automatic comparison of the wafer pattern against a CAD derived design model.

A system to automatically inspect wafers for pattern defects has recently been developed. With this apparatus, the patterns of two neighboring chips are converted into video signals, which are then electronically compared by sophisticated hybrid circuitry to determine any differences between them. The discrepancies, if any, are recognized as defects. The inspection results are processed with a built-in microcomputer and the defect coordinates are stored in memory. By accessing them, the wafer is moved into exact position for post-inspection confirmation and close examination of each defect by the operator through a microscope. The defective wafer pattern is also displayed on a video monitor. In addition, it is possible to draw a defect map by utilizing an X-Y plotter interfaced to the inspection system. The system is equipped with two inspection modes for maximum versatility. The video signal can be generated by either bright-field or dark-field imaging methods. The user may therefore select the mode most compatible to a specific wafer and its requirements. Typical applications of this system include: - to detect pattern defects on the finished wafer (after photoresist developing an e, etching) that may have occured during the various production processes. - to detect repeating defects resulting from inconsistencies on an arrayed reticle used in the wafer stepping process. (The importance of this feature will become increas-ingly evident as direct wafer steppers become the workhorses of the VLSI era.) - to monitor various processing factors, such as foreign particle contamination. The performance and efficiency of such an automatic wafer inspection system will undoubtedly lead to its replacing the current conventional method of manual microscopic examination by the human eye in the near future. This is supported by the inclusion of data collected by end users of this system.

There is a need for micro-pattern inspection of in-process wafers in order to monitor the ongoing pattern quality. In the context of volume wafer production, this need is currently being addressed by a variety of manual and semiautomated equipment. There is a continuing trend towards automation. A profile of current needs and practices, as well as possible future solutions, to pattern inspection and measurement has been developed after consulting with numerous individuals in the industry. Needs that will develop in the near future and some possible solutions are considered. Computer Aided Processing in the photo area is discussed. Pattern recognition is discussed as the inspection technology of the future and some results are shown.