Array Processors: New Architectures for Vision

Barry Isenstein; Scott Israel; Robert Frisch

doi:10.1117/12.950815

11 December 1985 Array Processors: New Architectures for Vision

Barry Isenstein, Scott Israel, Robert Frisch

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Proceedings Volume 0579, Intelligent Robots and Computer Vision IV; (1985) https://doi.org/10.1117/12.950815
Event: 1985 Cambridge Symposium, 1985, Cambridge, United States

Abstract

Array processors are being utilized in combination with microcomputers to provide high performance sophisticated processing for vision systems. Many manufacturers of vision systems have endeavored to build proprietary array processors because an off-the-shelf solution has not been available at a reasonable cost. The ZIP 3216 array processor has overcome the obstacles that have inhibited the widespread use in vision systems through hardware and software innovations. The architecture allows for easy integration of the array processor into almost any configuration and the software enviroment allows for easy customization of algorithms and efficient programming. Details of the programming environment will be discussed with emphasis on programming examples that eliminate the need for microprogramming the array processor. The features of the hardware design that allow for optimal speed and flexible integrating and upgrading capabilites, will also be discussed.

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Barry Isenstein, Scott Israel, and Robert Frisch "Array Processors: New Architectures for Vision", Proc. SPIE 0579, Intelligent Robots and Computer Vision IV, (11 December 1985); https://doi.org/10.1117/12.950815

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