The evolution of optical computing from simple arithmetic computing to complex logical computing closely parallels the transition of optical computing from the analog to the digital domain. The significance of optical crossbars in both arithmetic and logic-based optical computing systems is considered. An emphasis is placed on the unique ability of digital optical systems to implement extremely complex combinational logic structures. The significance of fan-in and fan-out is examined. The emergence of a new class of optoelectronic programmable logic arrays (PLA's) is discussed. A comparison of the potential operational limits of these devices to those of their electronic counterparts is presented.

ZnS interference filters can be used as optical logic elements to demonstrate symbolic substitution. A one-bit adder serves as a first step toward digital optical computing. Experimental implementation and related problems are addressed.

Spatial filtering is one of the main assets of optics for information processing. Here we review spatial filtering methods for performing binary logic operations. Many pairs of bits can be processed simultaneously. The input data are arranged in matrix form. The type of operation is usually homogeneous across the matrix. The input is encoded as a diffracting, as a scattering, or as a birefringent structure. Experimental results are shown. Applications of a described method for an optical adder are presented.

We discuss the capabilities of thermally induced refractive nonlinear logic devices and holographic optical elements for applications in all-optical signal processing and optical digital computing. Optimisation of switching speed and energy based on the present experimental data allow us to believe that operation rates as high as 1012 Hz-cm-2 are possible.

A description of a massively parallel optoelectronic CPU is presented. Integral to the design of the device is a complex fiberoptic interconnection pattern that serves as a portion of a programmable logic array. A rudimentary instruction set for this CPU is presented, and a corresponding interconnection pattern is derived. The system architecture is examined, and a physical realization of the CPU is presented. Operating characteristics at ten million instructions per second are detailed.

The associative processor architecture presented in this paper offers a new approach which takes advantage of developing optical logic devices as well as several beam-steering techniques. The beam-steering techniques (beam combination and beam expansion) rely on the interconnection capabilities of optics to perform several broadcasting functions which are useful in associative memory operations.

Optical-gate based waveguide matrix switches are described. The 4x4 single-mode switches are composed of optical gates and high-silica waveguide splitter, interconnection and combiner circuits. Two types of optical gates, a high-silica waveguide Mach-Zehnder interferometer gate and an InGaAsP laser-diode gate, are tested. The two types of preliminary 4x4 experimental switches exhibited more than 400 Mbit/s switch bandwidth. The optical waveguide gate matrix switch features point-to-multipoint switching and compact structure. The switch may be applied to optical signal processing systems as well as optical communication systems.

A directed graph processor and several optical realizations of its input symbolic feature vectors and the multi-processor operations required per node are given. This directed graph processor has advantages over tree and other hierarchical processors because of its large number of interconnections and its ability to adaptively add new nodes and restructure the graph. The use of the basic concepts of such a directed graph processor offer significant impact on: associative, symbolic, inference, feature space and correlation-based AI processors, as well as on knowledge base organization and procedural knowledge control of AI processors. Initial iconic alphanumeric data base results presented are most promising.

Optics has advantages for overcoming limitations arising when applying existing electronic technologies to real-time parallel computation. In particular, spatial light modulators (SLMs) permit simultaneous storage, multiplication, and/or complex interconnection. A simple diagnostic expert system uses Bayes theorem to recursively update the probabilities of various hypotheses given additional sensor input information. The 'a priori' probability matrices are stored in SLMs which provide matrix-vector multiplication and interconnection. High speed permits the optimum determination of which sensor should be polled next.

There. where many pattern recognition problems here the pattern's structural information is important. In these problems, a syntactic method of pattern recognition is of value. In this paper, both parallel syntactic pattern recognition algorithm and optical architecture implementation approaches are described. In particular, the applications of syntactic pattern recognition algorithm to shape classification are illustrated. A number of parallel optical syntactic pattern coding methods; a structural matched filter; an associative memory filter; and an optical symbolic substitution syntactic parser, are discussed.

In this paper we present a new approach to learning in a multilayer optical neural network which is based on holographically interconnected nonlinear Fabry-Perot etalons. The network can learn the interconnections that form a distributed representation of a desired pattern transformation operation. The interconnections are formed in an adaptive and self aligning fashion, as volume holographic gratings in photorefractive crystals. Parallel arrays of globally space integrated inner products diffracted by the interconnecting hologram illuminate arrays of nonlinear Fabry-Perot etalons for fast thresholding of the transformed patterns. A phase conjugated reference wave interferes with a backwards propagating error signal to form holographic interference patterns which are time integrated in the volume of the photorefractive crystal in order to slowly modify and learn the appropriate self aligning interconnections. A holographic implementation of a single layer perceptron learning procedure is presented that can be extendept ,to a multilayer learning network through an optical implementation of the backward error propagation (BEP) algorithm.

One of the fundamental problem areas in perception, cognition, and artificial intelligence concerns the characterization of the functional units into which perceptual and cognitive mechanisms group the patterned information that they process. A core issue concerns the context-sensitivity of these functional units, or the manner in which a grouping into functional units can depend upon the spatiotemporal patterning of all the signals being processed. Another core issue concerns the adaptive tuning of recognition mechanisms, and the manner in which such tuning can alter the groupings which emerge within a context containing familiar elements. Adaptive tuning of recognition processes is one of the mechanisms whereby representations become compressed, chunked, or unitized into coherent recognition codes through experience.

Recent advances in massively parallel optical and electronic neural network processing technology have made it plausible to consider the use of matched filter banks containing large numbers of individual filters as pattern classifiers for complex spatiotemporal pattern environments such as speech, sonar, radar, and advanced communications. This paper begins with all overview of how neural networks can be used to approximately implement such multidimensional matched filter banks. The "nearest matched filter" classifier is then formally defined. It is then noted that, given a statistically comprehensive set of filter templates, the nearest matched filter classifier will have near-Bayesian performance for spatiotemporal patterns. The combination of near-Bayesian classifier performance with the excellent performance of matched filtering in noise yields a powerful new classification technique. This adds additional interest to Grossberg's hypothesis that the mammalian cerebral cortex carries out local-in-time nearest matched filter classification of both auditory and visual sensory inputs as an initial step in sensory pattern recognition - which may help explain the almost instantaneous pattern recognition capabilities of animals.

The IBM Los Angeles Scientific Center has been studying the application of a parallel computational model, the Associative Network, or "AN", to computer vision problems. This work has led to the design of ANs that compute Boolean functions, convolution integrals, Gaussian filtered images, edge-enhanced images, region-growing algorithms, the Hough transform, and simple pattern recognition. Every computation has required a distinct approach to AN design, demonstrating the versatility of ANs. These application studies have shown that image processing transformations, often too slow to be practical on a sequential machine, can be executed rapidly with ANs.

In this paper non-Bayesian and heuristic approaches are applied to the well known problem of image segmentation. The two subproblems in segmentation that were considered were region merge and line detection. For the region merge problem, a comparison was made between the classical Bayes and fuzzy set based approach. Simulations, using a "block world" type real image, were implemented in ZETALISP on the Symbolics 3675 computer. They contrasted the proposed region merge method with the classical implementations. The performance measures of the classical line detection problem, using the Hough transform, are reinterpreted in a non-traditional framework using fuzzy sets and heuristics. Several alternative real-time optical Hough transform schemes are presented as well.

The basic concepts and definitions needed to understand the operations in Multiple-Valued Logic Systems are presented. The intent of this presentation is to acquaint the uninformed optical engineer about the characteristics of such a system. Since the author is not familiar with current optical techniques, there will be no attempt to make applications in optical systems.

Threshold logic, in which each input is weighted, has many theoretical advantages over the standard gate realization, such as reducing the number of gates, interconnections, and power dissipation. However, because of the difficult synthesis procedure and complicated circuit implementation, their use in the design of digital systems is almost nonexistant. In this study, three methods of NMOS realizations are discussed, and their advantages and shortcomings are explored. Also, the possibility of using the methods to realize multi-valued logic is examined.

The design and implementation of a high-precision, high fan-in, optoelectronic threshold gate is discussed. The device is entirely digital. It is capable of altering its internal weights and function dynamically to provide the equivalent of a programmable gate. External circuitry has been specially designed to provide intrinsic control variables, as well as ordinary input variables. A distinction between extrinsic control variables and intrinsic control variables is presented. Analogies to the operation of a central processing unit are considered. Physical fabrication details and operating characteristics at ten million instructions per second are discussed.

A topic of considerable interest in the design of digital switching functions is that of functional decomposition. Decomposition has been pursued by researchers in an attempt to determine more efficient techniques to implement switching functions. This topic is of interest to designers of both mult-valued and binary systems. This paper will introduce the topic and point out several approaches that have been taken.

Practical adaptations of existing acousto-optic processors are advanced which result in systems inherently capable of attaining accurate, high-speed linear analog numerical processing with realistic components and simple drive electronics. The systems presented are heterodyned space-integrating configurations driven by multiple diode laser sources. All signals in the systems are encoded on quadrature temporal carriers, allowing bipolar and complex-valued data to be processed. This also enables the diode lasers, acousto-optic cells, and output detectors to be used in their most inherently linear operating modes, and significantly reduces the effects of temperature and prior input data on the absolute accuracy obtained. Applications of such processors are considered.

While Spatial Light Modulator (SLM) based Expert Systems (ES) have been discussed before, the amount of knowledge that can be represented in this manner is very small. Combining SLM based ES with page oriented holographic memories not only cures this problem but also produces for optical ES a decisive advantage over optical ES.

The advantage of using the residue number system in content-addressable memories is explained. The implementations of addition and multiplication with these processors are presented. The conversion of residue numbers to their equivalent binary numbers is described. The direct implementation of an 8-bit adder with residue-based content-addressable memories is investigated.

This paper addresses some of the issues concerning the use of variable accuracy optical processors to improve the processing time required to obtain a high accuracy solution to a set of Linear Algebraic Equations (LAEs). We begin with a standard error analysis of the Steepest Descent iterative algorithm used to find the solution to the LAEs. This results in an expression relating the accuracy of the solution to the number of iterations and the inherent system accuracy in each mode of operation, along with the eigen-structure of the matrix describing the LAE. The accuracy at any iteration is a combination of terms representing the ideal algorithmic improvement plus the degradation due to processor inaccuracies. An evaluation of the proper number of iterations for processing in both low and high accuracy modes can be inferred through an examination of the tradeoffs in accuracy between these two terms. The expression is evaluated for several sample problems obtained from the Adaptive Phased Array Radar field. These results are then interpreted with respect to specific optical processing architectures.

A sample and hold technique is described by utilizing a newly observed cross modulation effect. In the modulation effect a light beam from a LED source is transmitted through a semi insulating GaAs sample. When an optical pulse hits the sample in the presence of a voltage pulse an enhanced absorption of LED light is observed after the optical pulse. The absorption is held by the duration of the voltage pulse. This effect can be utilized in spatial light modulators for serial to parallel data conversion and in many other applications involving electrically addressable memory.

This paper reports on the characterization of CMOS detectors for holographic optical interconnects in microcircuits. A VLSI temporal response system has been built, which has high-magnification viewing capabilities to facilitate identifying the sample area under investigation. A isolated photodiode and load circuit has been characterized to determine responsivity, response time and light spot positioning effects. The threshold of optical gate cells (OGC) incorporating the above detectors and a transistor inverter stage to couple to other circuitry has been determined. The rise time and fall time of the optical gate cells have also been determined experimentally. The results were compared with the results of SPICE simulation, and show satisfactory agreement. The time delay of optical gate cell output was thus determined to be 70 ns at 10 μW light input. Threshold power was 0.5 μW light input.

Dynamic global interconnections between processors in massively parallel computers are a highly desirable feature. Their implementation would greatly increase performance because large bandwidth interprocessor communication links may be reconfigured to match problem geometries. Global hardwiring of interconnects for large processor arrays is cumbersome, and present systems use rather tedious packet routing virtual interconnects. This report presents a novel design concept for a dynamic optical interconnect which would create a holographic interconnect between any two (or more) processors upon request. Each processor has a detector and a light source. A hologram may then be written into a nonlinear crystal which will diffract modulated light from a source at one processor to detectors at any other processors which desire that communication link. Writing is a two step process using a phase conjugate mirror and requiring the light sources of the involved processors to be mutually coherent. Preliminary analysis of this system along with an experimental proof of concept is discussed.

This paper discusses the need for 2-D multistage optical interconnection networks in parallel computing systems and demonstrates the benefits obtained from a 2-D multi-stage perfect shuffle network.

A through-the-backplane, circuit pack optical connector, utilizing a novel alignment mechani3m, is described. Up to 13 fibers can be interconnected in a space of 0.5" x 0.6" x 2.26". Average loss is 0.53 dB with 50/125 fiber. Laboratory tests with single mode fiber (8.3/125) in a modified connector have shown an average loss of about 0.7dB. All measurements were made without index matching material.

Given the crosstalk and loss of a single optical directional coupler, we predict the Signal-to-Noise Ratios (SNRs) of switches made from interconnected couplers. Of the seven 4x4 architectures simulated, three are strictly nonblocking, two are nonblocking in the wide sense, and two are rearrangeably nonblocking. The simulation models each coupler in an architecture, traces the signal and accumulates noise throughout the architecture, and gives the SNR at any output. For typical values of crosstalk per directional coupler, all of the 4x4 architectures compared here have good enough SNRs for non-cascaded use. The active splitter/active combiner and duobanyan switches have a large enough SNR to be cascaded without regeneration.

Wideband optical interconnections aver short distances require significantly less optical power (i.e. < 10 microwatts) than do long-haul communication links for which most laser diodes are designed. The current trend in laser diode development emphasizes high power and single mode operation. For local point-to-point interconnections where laser power dissipation is a primary concern (e.g., systems having many channels and interconnection to super-conducting electronics), low threshold operation is paramount, while mode quality is less important. Our approach to laser design has been redirected by these requirements for low power operation. We present measurements of low-threshold laser diodes at cryogenic temperatures and discuss the suitability of such devices for low power operation with super-conducting electronics. We also discuss laser diode design approaches which emphasize micropower operation.