The entire electronic materials market is continually pushed node over node. In the past, the progression of exposure wavelengths that enabled advancement against Moore’s law gave rise to new resist chemistries that would then undergo years of refinement and optimization to squeeze the maximum resolution and CD control from each platform. The push on materials for resolution and process latitude continues today, but these are becoming secondary to new focus areas such as the material contributions to edge placement error (LWR, CDU), planarization, gap filling, and etch selectivity. At the same time, these new materials must be introduced with lower and lower defect contributions. Originally, many materials suppliers focused mainly on supporting their customers with photoresist solutions within the electronic materials space. Today suppliers continue to develop new photoresists but have expanded into complementary segments such as organic underlayers, spin-on metal anti-reflective coatings, topcoats, a variety of shrinking and slimming approaches as well as CMP pads and slurries. Semiconductor integration of new materials from across the periodic table leads us to develop new wet-cleaning chemistries and even materials that self-assemble in bottoms up patterning. In parallel segments such as 2.5D and 3D packaging bring on new challenges in the space of advancing thick resists for plating applications and permanent spin on dielectrics. Additionally, advances in display technology needs, along with CMOS image sensors bring even further challenges to the materials suppliers. As our view within electronic materials expands, we have a unique perspective into how materials are influencing and shaping the electronic industry. This talk will present an overview with the long term vision of our future digital society including how electronics industry evolves and how materials fit into the larger picture.

This PDF file contains the front matter associated with SPIE Proceedings Volume 10144, including the Title Page, Copyright information, Table of Contents, Introduction (if any), and Conference Committee listing.

Imprint lithography has been shown to be a promising technique for replication of nano-scale features. Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate.

There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Included on the list are overlay, throughput and defectivity. The most demanding devices now require overlay of better than 4nm, 3 sigma. Throughput for an imprint tool is generally targeted at 80 wafers per hour. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices.

The purpose of this paper is to report the status of throughput and defectivity work and to describe the progress made in addressing overlay for advanced devices. In order to address high order corrections, a high order distortion correction (HODC) system is introduced. The combination of applying magnification actuation to the mask, and temperature correction to the wafer is described in detail and examples are presented for the correction of K7, K11 and K17 distortions as well as distortions on actual device wafers.

A low cost alternative lithographic technology is desired to meet the decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the candidates for alternative lithographic technologies.^[1][2][3] NIL has such advantages as good resolution, critical dimension (CD) uniformity and low line edge roughness (LER). On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the HVM, it is necessary to overcome these three challenges simultaneously.^[4]-[12] In our previous study, we have reported a dramatic improvement in NIL process defectivity on a pilot line tool, FPA-1100 NZ2. We have described that the NIL process for 2x nm half pitch is getting closer to the target of HVM.^[12] In this study, we report the recent evaluation of the NIL process performance to judge the applicability of NIL to memory device fabrications. In detail, the CD uniformity and LER are found to be less than 2nm. The overlay accuracy of the test device is less than 7nm. A defectivity level of below 1pcs./cm² has been achieved at a throughput of 15 wafers per hour.

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is cross-linked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate.

Criteria specific to any lithographic process for the semiconductor industry include overlay, throughput and defectivity. The purpose of this paper is to describe the technology advancements made in the reduction of particle adders in an imprint tool.

Hard particles on a wafer or mask create the possibility of creating a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, test stand results demonstrate the potential for extending mask life to better than 1000 wafers.

Imprint lithography is a promising technology for replication of nano-scale features. For semiconductor device applications, Canon deposits a low viscosity resist on a field by field basis using jetting technology. A patterned mask is lowered into the resist fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate.

There are two critical components to meeting throughput requirements for imprint lithography. Using a similar approach to what is already done for many deposition and etch processes, imprint stations can be clustered to enhance throughput. The FPA-1200NZ2C is a four station cluster system designed for high volume manufacturing.

For a single station, throughput includes overhead, resist dispense, resist fill time (or spread time), exposure and separation. Resist exposure time and mask/wafer separation are well understood processing steps with typical durations on the order of 0.10 to 0.20 seconds. To achieve a total process throughput of 17 wafers per hour (wph) for a single station, it is necessary to complete the fluid fill step in 1.2 seconds. For a throughput of 20 wph, fill time must be reduced to only one 1.1 seconds.

There are several parameters that can impact resist filling. Key parameters include resist drop volume (smaller is better), system controls (which address drop spreading after jetting), Design for Imprint or DFI (to accelerate drop spreading) and material engineering (to promote wetting between the resist and underlying adhesion layer). In addition, it is mandatory to maintain fast filling, even for edge field imprinting. In this paper, we address the improvements made in all of these parameters to first enable a 1.20 second filling process for a device like pattern and have demonstrated this capability for both full fields and edge fields. Non-fill defectivity is well under 1.0 defects/cm² for both field types. Next, by further reducing drop volume and optimizing drop patterns, a fill time of 1.1 seconds was demonstrated.

Nanoimprint lithography (NIL) is a promising technique for fine-patterning with a lower cost than other lithography techniques such as EUV or immersion with multi-patterning. NIL has the potential of "single" patterning for both line patterns and hole patterns with a half-pitch of less than 20nm. NIL tools for semiconductor manufacturing employ die-by-die alignment system with moiré fringe detection which gives alignment measurement accuracy of below 1nm.

In this paper we describe the evaluation results of NIL the overlay performance using an up-to-date NIL tool for 300mm wafer. We show the progress of both "NIL-to-NIL" and "NIL-to-optical tool" distortion matching techniques. From these analyses based on actual NIL overlay data, we discuss the possibility of NIL overlay evolution to realize an on-product overlay accuracy to 3nm and beyond.

We have established a non-contact polishing process for thermoplastic, polymeric microlenses and –prisms with dimensions of up to 50 μm, including sharp convex tips and rims with sub-μm details. The required 3D master structures were fabricated using direct laser-writing lithography with two-photon absorption. Master structures were replicated into poly(methyl methacrylate) through a poly(dimethyl siloxane) intermediate copying step and exposed with 172 nm UV light. Due to the reduction of glass transition temperature in a surface-confined layer, roughness in the range of more than 100 nm could subsequently be smoothed-out to below 10 nm by annealing the surface by heating.

Fabrication processes that microelectronic developed for Integrated circuit (IC) technologies for decades, do not meet the new emerging structuration’s requirements, in particular non-IC related technologies one, such as MEMS/NEMS, Micro-Fluidics, photovoltaics, lenses. Actually complex 3D structuration requires complex lithography patterning approaches such as gray-scale electron beam lithography, laser ablation, focused ion beam lithography, two photon polymerization. It is now challenging to find cheaper and easiest technique to achieve 3D structures.

In this work, we propose a straightforward process to realize 3D structuration, intended for silicon based materials (Si, SiN, SiOCH). This structuration technique is based on nano-imprint lithography (NIL), ion implantation and selective wet etching. In a first step a pattern is performed by lithography on a substrate, then ion implantation is realized through a resist mask in order to create localized modifications in the material, thus the pattern is transferred into the subjacent layer. Finally, after the resist stripping, a selective wet etching is carried out to remove selectively the modified material regarding the non-modified one.

In this paper, we will first present results achieved with simple 2D line array pattern processed either on Silicon or SiOCH samples. This step have been carried out to demonstrate the feasibility of this new structuration process. SEM pictures reveals that “infinite” selectivity between the implanted areas versus the non-implanted one could be achieved. We will show that a key combination between the type of implanted ion species and wet etching chemistries is required to obtain such results.

The mechanisms understanding involved during both implantation and wet etching processes will also be presented through fine characterizations with Photoluminescence, Raman and Secondary Ion Mass Spectrometry (SIMS) for silicon samples, and ellipso-porosimetry and Fourier Transform InfraRed spectroscopy (FTIR) for SiOCH samples. Finally the benefit of this new patterning approach will be presented on 3D patterns structures.

Nanoimprint lithography, NIL, is gathering much attention as one of the most potential candidates for the next generation lithography for semiconductor. This technology needs no pattern data modification for exposure, simpler exposure system, and single step patterning process without any coat/develop truck, and has potential of cost effective patterning rather than very complex optical lithography and/or EUV lithography. NIL working templates are made by the replication of the EB written high quality master templates. Fabrication of high resolution master templates is one of the most important issues. Since NIL is 1:1 pattern transfer process, master templates have 4 times higher resolution compared with photomasks. Another key is to maintain the quality of the master templates in replication process. NIL process is applied for the template replication and this imprint process determines most of the performance of the replicated templates. Expectations to the NIL are not only high resolution line and spaces but also the contact hole layer application. Conventional ArF-i lithography has a certain limit in size and pitch for contact hole fabrication. On the other hand, NIL has good pattern fidelity for contact hole fabrication at smaller sizes and pitches compared with conventional optical lithography. Regarding the tone of the templates for contact hole, there are the possibilities of both tone, the hole template and the pillar template, depending on the processes of the wafer side. We have succeeded to fabricate both types of templates at 2xnm in size. In this presentation, we will be discussing fabrication or our replica template for the contact hole layer application. Both tone of the template fabrication will be presented as well as the performance of the replica templates. We will also discuss the resolution improvement of the hole master templates by using various e-beam exposure technologies.

Directed Self-Assembly is the method by which a self-assembly polymer is forced to follow a desired geometry defined or influenced by a guiding pattern. Such guiding pattern uses surface potentials, confinement or both to achieve polymer configurations that result in circuit-relevant topologies, which can be patterned onto a substrate.

Chemo, and grapho epitaxy of lines and space structures are now routinely inspected at full wafer level to understand the defectivity limits of the materials and their maximum resolution. In the same manner, there is a deeper understanding about the formation of cylinders using grapho-epitaxy processes. Academia has also contributed by developing methods that help reduce the number of masks in advanced nodes by “combining” DSA-compatible groups, thus reducing the total cost of the process.

From the point of view of EDA, new tools are required when a technology is adopted, and most technologies are adopted when they show a clear cost-benefit over alternative techniques. In addition, years of EDA development have led to the creation of very flexible toolkits that permit rapid prototyping and evaluation of new process alternatives. With the development of high-chi materials, and by moving away of the well characterized PS-PMMA systems, as well as novel integrations in the substrates that work in tandem with diblock copolymer systems, it is necessary to assess any new requirements that may or may not need custom tools to support such processes.

Hybrid DSA processes (which contain both chemo and grapho elements), are currently being investigated as possible contenders for sub-5nm process techniques. Because such processes permit the re-distribution of discontinuities in the regular arrays between the substrate and a cut operation, they have the potential to extend the number of applications for DSA.

This paper illustrates the reason as to why some DSA processes can be supported by existing rules and technology, while other processes require the development of highly customized correction tools and models. It also illustrates how developing DSA cannot be done in isolation, and it requires the full collaboration of EDA, Material’s suppliers, Manufacturing equipment, Metrology, and electronic manufacturers.

To a major candidate and beyond, directed self-assembly (DSA) lithography is investigated on DRAM contact-hole fabrication. We perform a systematic study about behavior of asymmetric PS-b-PMMA block copolymers (BCP) within pillar confinement for DSA and find that selectively removed PMMA contact domain has a different morphology according to chemically modified pillar surfaces. We calculate the perturbation of PMMA contacts by pillar diameter using free energy magnitude model. This established model provides practical engineering insight for present pillar scheme and future graphoepitaxial self-assembly techniques for semiconductor DSA procedure.

Directed Self Assembly (DSA) has emerged as one of the most compelling next generation patterning techniques for sub-7nm via or contact layers. A key issue in enabling DSA as a mainstream patterning technique is the generation of grapho-epitaxy based guiding pattern (GP) shapes to assemble the contact patterns on target with high fidelity and resolution. Current GP generation is mostly empirical, and limited to a very small number of via configurations. In this paper, we propose the first model-based GP synthesis algorithm and methodology for on-target and robust DSA, on general via pattern configurations. The final post-RET printed GPs derived from our original synthesized GPs are resilient to process variations and continue to maintain the same DSA fidelity in terms of placement error and target shape.

Direct Optimization (DO) of a 3D DSA model is a more optimal approach to a DTCO study in terms of accuracy and speed compared to a Cahn Hilliard Equation solver. DO’s shorter run time (10X to 100X faster) and linear scaling makes it scalable to the area required for a DTCO study. However, the lack of temporal data output, as opposed to prior art, requires a new calibration method. The new method involves a specific set of calibration patterns. The calibration pattern’s design is extremely important when temporal data is absent to obtain robust model parameters. A model calibrated to a Hybrid DSA system with a set of device-relevant constructs indicates the effectiveness of using nontemporal data. Preliminary model prediction using programmed defects on chemo-epitaxy shows encouraging results and agree qualitatively well with theoretical predictions from a strong segregation theory.

Maskless lithography using parallel electron beamlets is a promising solution for next generation scalable maskless nanolithography. Researchers have focused on this goal but have been unable to find a robust technology to generate and control high-quality electron beamlets with satisfactory brightness and uniformity. In this work, we will aim to address this challenge by developing a revolutionary surface-plasmon-enhanced-photoemission (SPEP) technology to generate massively-parallel electron beamlets for maskless nanolithography. The new technology is built upon our recent breakthroughs in plasmonic lenses, which will be used to excite and focus surface plasmons to generate massively-parallel electron beamlets through photoemission. Specifically, the proposed SPEP device consists of an array of plasmonic lens and electrostatic micro-lens pairs, each pair independently producing an electron beamlet. During lithography, a spatial optical modulator will dynamically project light onto individual plasmonic lenses to control the switching and brightness of electron beamlets. The photons incident onto each plasmonic lens are concentrated into a diffraction-unlimited spot as localized surface plasmons to excite the local electrons to near their vacuum levels. Meanwhile, the electrostatic micro-lens extracts the excited electrons to form a focused beamlet, which can be rastered across a wafer to perform lithography. Studies showed that surface plasmons can enhance the photoemission by orders of magnitudes. This SPEP technology can scale up the maskless lithography process to write at wafers per hour. In this talk, we will report the mechanism of the strong electron-photon couplings and the locally enhanced photoexcitation, design of a SPEP device, overview of our proof-of-concept study, and demonstrated parallel lithography of 20-50 nm features.

In this study, a simulation analysis of a miniaturized electron optics for the Multi-Column Massively Parallel Electron Beam Writing system is demonstrated. Analytical evaluation of space charge effect with prototype Massively Parallel Electron Beam Writing (MPEBW) system showed 2.86 nm blur in radius occurs on each beam with a convergence half angle of 3 mrad. The angle of each beam was increased to 10 mrad to reduce the space charge effect, the coulomb blur amount can be kept to less than 1 nm in radius. However, there was limitation to increasing the angle due to a spherical aberration. Since the beam current density from the electron emitter array in the prototype MPEBW system was 100 μA/cm² and the total beam current was 1μA with 100×100 array of 10μm square emitter, the influence of coulomb blur was small. By contrast, considerably increasing the number of beams and the beam current are planned in near future in MPEBW. The coulomb blur and other aberrations will not be controlled by merely adjusting the beam convergence angle. In order to increase total beam current, miniaturized electron optics have been designed for Multi-beam+Multi-column system. Reduction lens in the designed miniaturized electron optics with crossover free to reduce the influence of coulomb repulsion with narrow convergence half angle. Unlike conventional methods, the electron beams as principal rays do not intersect at one point, so even if the beam becomes extremely narrow, the coulomb repulsion effect does not increase at the crossover area. The reduction of the entire size of parallel beams in the designed electron optics was confirmed by simulation software. The simulation results showed that least confusion disk of 6.5 nm size was obtained at the beam convergence half angles of 3 mrad corresponding to the incident beam of ±0.1 mrad divergence angle. It showed that the miniaturized electron optics was suitable for 10 nm order EB writing. The crossover free electron optics of the miniaturized electron optics is possible due to dispersing the intersection points of the principal rays by a combination of a concentric electron optics and a tapered lens electrode of the reduction lens.

Mapper Lithography has introduced its first product, the FLX–1200, which is installed at CEA-Leti in Grenoble (France). This is a mask less lithography system, based on massively parallel electron-beam writing with high-speed optical data transport for switching the electron beams. This FLX platform is initially targeted for 1 wph performance for 28 nm technology nodes, but can also be used for less demanding imaging. The electron source currently integrated is capable of scaling to 10 wph at the same resolution performance, which will be implemented by gradually upgrading the illumination optics. The system has an optical alignment system enabling mix-and-match with optical 193 nm immersion systems using standard NVSM marks. The tool at CEA-Leti is in-line with a Sokudo Duo clean track. Mapper Lithography and CEA-Leti are working in collaboration to develop turnkey solution for specific applications. At previous conferences we have presented imaging results including 28nm node resolution, cross wafer CDu of 2.5nm 3 and a throughput of half a wafer per hour, overhead times included. At this conference we will present results regarding the overlay performance of the FLX-1200. In figure 2 an initial result towards measuring the overlay performance of the FLX-1200 is shown. We have exposed a wafer twice without unloading the wafer in between exposures. In the first exposure half of a dense dot array is exposed. In the second exposure the remainder of the dense dot array is exposed. After development the wafer has been inspected using a CD-SEM at 480 locations distributed over an area of 100mm x 100mm. For each SEM image the shift of the pattern written in the first exposure relative to the pattern written in the second exposure is measured. Cross wafer this shift is 7 nm u+3s in X and 5 nm u+3s in Y. The next step is to evaluate the impact of unloading and loading of the wafer in between exposures. At the conference the latest results will be presented.

DSA patterning is a promising solution for advanced lithography as a complementary technique to standard and future lithographic technologies. In this work, we focused on DSA grapho-epitaxy process-flow dedicated for contact hole applications using polystyrene-b-poly(methyl methacrylate) (PS-b-PMMA) block copolymers. We investigated the impact on the DSA performances of the surface affinity of a guiding pattern design by ArF immersion lithography. The objective was to control and reduce the polymer residue at the bottom of the guiding pattern cavities since it can lead to lower a DSA-related defectivity after subsequent transfer of the DSA pattern. For this purpose, the DSA performances were evaluated as a function of the template surface affinity properties. The surface affinities were customized to enhance DSA performances for a PS-b-PMMA block copolymer (intrinsic period 35nm, cylindrical morphology) by monitoring three main key parameters: the hole open yield (HOY), the critical dimension uniformity (CDU-3σ) and the placement error (PE-3σ). Scanning transmission electron microscopy (STEM) was conjointly carried out on the optimized wafers to characterize the residual polymer thickness after PMMA removal. The best DSA process performances (i.e., hole open yield: 100%, CDU-3σ: 1.3nm and PE-3σ: 1.3nm) were achieved with a thickness polymer residue of 7 nm. In addition, the DSA-related defectivity investigation performed by review-SEM enabled us to achieve a dense (pitch 120nm) contact area superior to 0.01mm² free of DSA-related defects. This result represents more than 6x105 SEM-inspected valid contacts, attesting the progress achieved over the last years and witnessing the maturity of the DSA in the case of contact holes shrink application.

Directed self-assembly (DSA) has been investigated over the past few years as the candidate for next generation lithography. Especially, sub 20nm line and space patterns obtained by chemo-epitaxy process are expected to apply to DRAM active area, Logic fin and narrow metal patterns. One of the biggest advantages of DSA lines is that the pattern pitch is decided by the specific factors of the block copolymer, and it indeed the small pitch walking as a consequence. However, the generating mechanism of the DSA pattern defect is still not cleared^1-4 and the line edge roughness (LER) is not overtaken self- aligned quadruple patterning (SAQP).

In this report, we present the latest results regarding the defect reduction and LER improvement work regarding chemoepitaxy line and space pattern. In addition, we introduce the result of application of chemical epitaxy process to hole pattern.

One of technical issues of directed self-assembly lithography is extremely narrow patterning range. It is really difficult to make not only smaller patterns (pitch of less than 30nm) because of self-assembling limit but also middle patterns (pitch of more than 60nm) because of material synthesis issues. This paper describes wide–range directed self-assembly lithography which enables not only narrow patterns but also wide patterns using newly developed block copolymer. One block of the new block copolymer is easily metalized selectively by metalize technology and it is confirmed that dry etching resistance is markedly improved.

In this paper the rules-based correction strategies for the nanoimprint lithography (NIL) technology are addressed using complete Scanning Electron Microscopy (SEM) characterizations. Performed onto 200 mm wafers imprinted with the HERCULES NIL equipment platform, Critical Dimension (CD) uniformity analyses are used to measure the evolution of lines and spaces features dimensions from the master to 50 consecutive imprints. The work brings focus on sub micrometer resolution features with duty cycles from 3 to 7. The silicon masters were manufactured with 193 optical lithography and dry etching and were fully characterized prior to the imprint process. Repeatability tests were performed over 50 wafers for two different processes to collect statistical and comparative data. The data revealed that the CD evolutions can be modelled by quadratic functions with respect to the number of imprints and feature dimension (CD and pitch) on the master. These models are used to establish the rules-based corrections for lines arrays in the scope of nanoimprint master manufacturing, and it opens the discussion on the process monitoring through metrology for the nanoimprint soft stamp technologies.

Technologies for pattern fabrication using imprint process are being developed for various devices. Nanoimpirnt lithography (NIL) is an attractive and promising candidate for its pattern fidelity toward finer device fabrication without using double patterning. To apply smaller pattern size device, layout dependent hotspots becomes a significant issue, so design for manufacturing (DFM) flow considering imprint process has to be prepared. In this paper, focused on fine resist spread, RLT (Residual Layer Thickness) uniformity improvement utilizing simulation is demonstrated and resist drop compliance check flow is proposed

Directed Self Assembly (DSA) of block-copolymers (BCPs) used as a complementary technique to the 193nm immersion lithography has demonstrated sub-10nm node applications in both via and line/space patterning. We propose however to study the performance of graphoepitaxy which allows DSA with thicker initial BCP layer, higher multiplication factors and stronger orientation control of lamellae. The aim of this work is to use the 300mm pilot line available at LETI and Arkema’s advanced materials to evaluate the performances of a novel graphoepitaxy process based on the work on a 38nm period lamellar PS-b-PMMA (L38) reported before.

Since multi patterning with spacer was introduced in NAND flash memory¹, multi patterning with spacer has been a promising solution to overcome the resolution limit. However, the increase in process cost of multi patterning with spacer must be a serious burden to device manufacturers as half pitch of patterns gets smaller.^{2, 3} Even though Nano Imprint Lithography (NIL) has been considered as one of strong candidates to avoid cost issue of multi patterning with spacer, there are still negative viewpoints; template damage induced from particles between template and wafer, overlay degradation induced from shear force between template and wafer, and throughput loss induced from dispensing and spreading resist droplet. Jet and Flash Imprint Lithography (J-FIL^{4, 5, 6}) has contributed to throughput improvement, but still has these above problems. J-FIL consists of 5 steps; dispense of resist droplets on wafer, imprinting template on wafer, filling the gap between template and wafer with resist, UV curing, and separation of template from wafer. If dispensing resist droplets by inkjet is replaced with coating resist at spin coater, additional progress in NIL can be achieved. Template damage from particle can be suppressed by thick resist which is spin-coated at spin coater and covers most of particles on wafer, shear force between template and wafer can be minimized with thick resist, and finally additional throughput enhancement can be achieved by skipping dispense of resist droplets on wafer. On the other hand, spin-coat-based NIL has side effect such as pattern collapse which comes from high separation energy of resist. It is expected that pattern collapse can be improved by the development of resist with low separation energy.

Nano-imprint lithography (NIL) is an emerging high-resolution parallel patterning method, mainly aimed towards fields in which high-end photolithography methods are costly and do not provide sufficient resolution at reasonable throughput. High resolution stamp patterning can currently be performed by electron and ion dual beam system. By scanning the focused electron beam (or ion beam) while injecting a suitable organometallic precursor gas around the location of e-beam (or ion beam) and just above the stamp substrate, a high-density and high-uniformity hard mask for subsequent etching without use proximity-effect correction techniques. Furthermore, this technique can also directly deposit a metal pattern for interconnect or a dielectric pattern on NIL stamp without the need for separate metal or dielectric deposition, photoresist etch-mask, and etching processes. FEI Helios Nano Lab™ 1200 and Nova Nano Lab™ 600 dual beam system are used in this work for NIL stamp inspection and fabrication.

Directed Self Assembly (DSA) has emerged as one of the most compelling next generation patterning techniques for sub-7nm via or contact layers. A key issue in enabling DSA as a mainstream patterning technique is the generation of grapho-epitaxy based guiding pattern (GP) shapes to assemble the contact patterns on target with high fidelity and resolution. Current GP generation is mostly empirical, and limited to a very small number of via configurations. In this paper, we propose the first model-based GP synthesis algorithm and methodology for on-target and robust DSA, on general via pattern configurations. The final post-RET printed GPs derived from our original synthesized GPs are resilient to process variations and continue to maintain the same DSA fidelity in terms of placement error and target shape.