This PDF file contains the front matter associated with SPIE Proceedings Volume 10148 including the Title Page, Copyright information, Table of Contents, Introduction, and Conference Committee listing.

Making standards cells smaller by lowering the cell height from 7.5 tracks to 6 tracks for the same set of ground rules is an efficient way to reduce area for high density digital IP blocks without increasing wafer cost. Denser cells however also imply a higher pin density and possible more routing congestion because of that. In Place and Route phase, this limits the cell density (a.k.a. utilization) that can be reached without design rule violations. This study shows that 6-track cells (192nm high) and smart routing results in up to 60% lower area than 7.5-track cells in N5 technology. Standard cells have been created for 7.5T and 6T cells in N5 technology (poly pitch 42nm, metal pitch 32nm). The cells use a first horizontal routing layer (Mint) and vertical M1 for 1D intra-cell routing as much as possible. Place and route was performed on an opencores LDPC decoder. Various cell architectures and place and route optimizations are used to scale down the cell area and improve density. Most are not process optimizations, but optimized cell architectures and routing methods: • Open M1: M1 is removed as much as possible. This allows the router to use M1 for inter-cell routing in dense areas. • Routing in Mint: With open M1 the router can also use Mint to extend pins to access nearby free M1 tracks in congested areas. • Outbound rail: The 7.5T cells have inbound VDD/VSS rails in Mint for easy supply tapping. Moving the Mint rail outbound and shared between cells is required to enable lower track height cells. • Vertical Power distribution network (PDN): in 6T cells too many horizontal tracks would be consumed by the wide M2 rail. Mint is used instead combined with a vertical PDN in M1. • Self-Aligned Gate Contact allows to contact the gate on top of active fins. Any Mint track then can contact a gate, reducing cell area considerably. • Partially landing Mint Via trench: In 6T cells, a continuous Via trench underneath the Mint rail is used. This via partially lands on M0A to relax tip-to-tip requirements. • Relaxed M2 pitch: When pin access is handled in Mint and M1, this allows for a relaxed M2 pitch (48nm) with cheaper double patterning. To avoid horizontal routing layer congestion with the smaller cells, the 6T cells depend on the vertical PDN and open M1 to improve routability and pin access. Already in 7.5T cells, open M1 and vertical PDN help to improve routable utilization from 50% with closed M1 to 85% maximum. Moving to 6T cells, the combination of reduced cell area and high 85% utilization of result in a 60% area reduction vs the original 7.5T cells. We have shown that combining 6-track cells and smart routing results in up to 60% lower area than 7.5-track cells in N5 technology. Open M1 and vertical PDN are main area boosters for any cell architecture, boosting utilization from 50% to 85% already for the 7.5T cells.

A pattern-based methodology for optimizing SADP-compliant layout designs is developed based on identifying cut mask patterns and replacing them with pre-characterized fixing solutions. A pattern-based library of difficult-tomanufacture cut patterns with pre-characterized fixing solutions is built. A pattern-based engine searches for matching patterns in the decomposed layouts. When a match is found, the engine opportunistically replaces the detected pattern with a pre-characterized fixing solution. The methodology was demonstrated on a 7nm routed metal2 block. A small library of 30 cut patterns increased the number of more manufacturable cuts by 38% and metal-via enclosure by 13% with a small parasitic capacitance impact of 0.3%.

Topological pattern-based methods for analyzing IC physical design complexity and scoring resulting patterns to identify risky patterns have emerged as powerful tools for identifying important trends and comparing different designs. In this paper, previous work is extended to include analysis of layouts designed for the 7nm technology generation. A comparison of pattern complexity trends with respect to previous generations is made. In addition to identifying topological patterns that are unique to a particular design, novel techniques are proposed for scoring those patterns based on potential yield risk factors to find patterns that pose the highest risk.

Redundant via (RV) insertion is employed to enhance via manufacturability, and has been extensively studied. Self-aligned double patterning (SADP) process, brings a new challenge to RV insertion since newly created cut for each RV insertion has to be taken care of. Specifically, when a cut for RV, which we simply call RV-cut, is formed, cut conflict may occur with nearby line-end cuts, which results in a decrease in RV candidates. We introduce cut merging to reduce the number of cut conflicts; merged cuts are processed with stitch using litho-etch-litho-etch (LELE) multi-patterning method. In this paper, we propose a new RV insertion method with cut merging in SADP for the first time. In our experiments, a simple RV insertion yields 55.3% vias to receives RVs; our proposed method that considers cut merging increases that number to 69.6% on average of test circuits.

With the advancement of VLSI technology nodes, light diffraction caused lithographic hotspots have become a serious problem affecting manufacture yield. Lithography hotspot detection at the post-OPC stage is imperative to check potential circuit failures when transferring designed patterns onto silicon wafers. Although conventional lithography hotspot detection methods, such as machine learning, have gained satisfactory performance, with extreme scaling of transistor feature size and more and more complicated layout patterns, conventional methodologies may suffer from performance degradation. For example, manual or ad hoc feature extraction in a machine learning framework may lose important information when predicting potential errors in ultra-large-scale integrated circuit masks. In this paper, we present a deep convolutional neural network (CNN) targeting representative feature learning in lithography hotspot detection. We carefully analyze impact and effectiveness of different CNN hyper-parameters, through which a hotspot-detection-oriented neural network model is established. Because hotspot patterns are always minorities in VLSI mask design, the training data set is highly imbalanced. In this situation, a neural network is no longer reliable, because a trained model with high classification accuracy may still suffer from high false negative results (missing hotspots), which is fatal in hotspot detection problems. To address the imbalance problem, we further apply minority upsampling and random-mirror flipping before training the network. Experimental results show that our proposed neural network model achieves highly comparable or better performance on the ICCAD 2012 contest benchmark compared to state-of-the-art hotspot detectors based on deep or representative machine leaning.

A typical new IC design has millions of layout configurations, not seen on previous product or test chip designs. Knowing the disposition of each and every configuration, problematic or not, is the key to optimizing design for yield. In this paper, we present a method to systematically characterize the configuration coverage of any layout. Coverage can be compared between designs, and configurations for which there is a lack of coverage can also be computed. When combined with simulation, metrology, and defect data for some configurations, graph search and machine learning algorithms can be applied to optimize designs for manufacturing yield.

Many different advanced devices and design layers currently employ double patterning technology (DPT) as a means to overcome lithographic and OPC limitations at low k1 values. Certainly device layers with k1 value below 0.25 require DPT or other pitch splitting methodologies. DPT has also been used to improve patterning of certain device layers with k1 values slightly above 0.25, due to the difficulty of achieving sufficient pattern fidelity with only a single exposure. Unfortunately, this broad adoption of DPT also came with a significant increase in patterning process cost. In this paper, we discuss the development of a single patterning technology process using an integrated Inverse Lithography Technology (ILT) flow for mask synthesis. A single pattering technology flow will reduce the manufacturing cost for a k1 > 0.25 full chip random contact layer in a memory device by replacing the more expensive DPT process with ILT flow, while also maintaining good lithographic production quality and manufacturable OPC/RET production metrics.

This new integrated flow consists of applying ILT to the difficult core region and traditional rule-based assist features (RBAFs) with OPC to the peripheral region of a DRAM contact layer. Comparisons of wafer results between the ILT process and the non-ILT process showed the lithographic benefits of ILT and its ability to enable a robust single patterning process for this low-k1 device layer. Advanced modeling with a negative tone develop (NTD) process achieved the accuracy levels needed for ILT to control feature shapes through dose and focus. Details of these afore mentioned results will be described in the paper.

As technology node shrinks down, hotspots, i.e. patterning failures on wafer after etching process, become an inevitable problem. The main cause of such hotspots is low contrast of aerial image. There are several methods that can improve aerial image contrast such as SRAF insertion and OPC. However, it is difficult to fix all hotspots by applying only SRAF and OPC in advanced technology node. This paper proposes a new post-layout optimization method, before SRAF and OPC, based on SOCS kernel for improving aerial image contrast and reducing hotspots. Experimental results show average 4nm PV-band improvement, as a result of contrast improvement.

In this paper, we present a design technology co-optimization (DTCO) flow to pattern self-aligned via (SAV) using two masks with grapho-epitaxy of lamella BCP and 193i for sub-7nm design. We show that it is necessary to consider both metal and via layers at the same time in creating design rules with process variations. Due to lamella DSA’s own characteristics, it can be easily applied in dense memory or SRAM applications for SAV patterning using traditional single-material metal hard mask. However, to achieve two-mask SAV solution for logic applications, we need to apply alternating hard mask in metal to cut lamella DSA patterns without compromising the technology scaling.

In recent years, directed self-assembly (DSA) has demonstrated tremendous potential to reduce cost for multiple patterning with fewer masks, especially for via patterning. DSA is considered as one of the next generation lithography candidates or complementary lithography techniques to extend 193i lithography further for the sub- 7 nm nodes. In this work, we focus on the simultaneous DSA guiding template assignment and decomposition with DSA and double patterning (DSA-DP) hybrid lithography for 7nm technology node. We first analyze the placement error of DSA patterns with different shapes and sizes. We then propose a graph-based approach to reduce the problem size and solve the problem more efficiently without affecting the optimality of the results. The experimental results demonstrate that we can achieve a 50% reduction in both the number of variables and constraints compared to previous work, which leads to a 50X speed up in runtime.

Directed Self Assembly (DSA) is a very promising patterning technology for the sub-7nm technology nodes, especially for via/contact layers. In the Graphoepitaxy type of DSA, a complementary lithography technique is used to print the guiding templates, where the Block Copolymer (BCP) phase-separates into regular structures. Accordingly, the design-friendliness of a DSA-based technology is affected by several factors: the complementary lithography technique, the legal guiding templates, the number of masks/exposures used to print the templates, the related design rules, the forbidden patterns (hotspots) and the characteristics of the BCP. Thus, foundries have a huge number of choices to make for a future DSA-based technology, affecting the design-friendliness and the cost of the technology. In this paper, we propose a framework for DSA technology path-finding, for via layers, to be used by the foundry as part of Design and Technology Co-optimization (DTCO). The framework optimally evaluates a DSA-based technology where an arbitrary lithography technique is used to print the guiding templates, possibly using many masks/exposures and provides a design-friendliness metric. The framework is used to evaluate technologies like DSA+193nm Immersion (193i) Lithography, DSA+Extreme Ultraviolet (EUV) and DSA+ Self-Aligned Double Patterning. For example, one study showed that one mask of EUV in a DSA+EUV technology can replace three masks of 193i in a DSA+193i technology.

In the pursuit of alternatives to traditional optical lithography, block copolymer directed self-assembly (DSA) has emerged as a low-cost, high-throughput option. However, issues of defectivity have hampered DSA's viability for large-scale patterning. Recent studies have shown copolymer fill level to be a crucial factor in defectivity, as template overfill can result in malformed DSA structures and poor LCDU after etching. For this reason, it is previously demonstrated the use of sub-DSA resolution assist features (SDRAFs) as a method of evening out template density. In this work, we propose an algorithm to place SDRAFs in random logic contact/via layouts. By adopting this SDRAF placement scheme, we can significantly improve the density unevenness and the resources used are also optimized. This is the first work to investigate the placement of SDRAFs in order to mitigate the DSA density variation problem, and it can be adopted for the mass deployment of DSA.

As pitch scaling is becoming constrained not only by lithographic resolution limits but alos by fundamental device and interconnect challenges the semiconductor industry has turned to cell-height reduction as a means of achieving competitive area scaling. The risk in using cell-height reduction to compensate for insufficient pitch scaling is that place- and-route inefficiencies caused by wiring congestion at the block level of the design can easily eliminate any area scaling gains made at the cell level of the design. This paper shows how careful cell-architecture optimization, physical design methodology changes, and place-and-route innovations have led to competitive block level area scaling for 7nm technology nodes and beyond. Data is presented to show that an entire node’s worth of scaling can be achieved through these comprehensive design-technology co-optimization efforts.

Static Random Access Memory (SRAM) cells are used together with logic standard cells as the benchmark to develop the process flow for new logic technologies. In order to achieve successful integration of Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) as area efficient higher level embedded cache, it also needs to be included as a benchmark. The simple cell structure of STT-MRAM brings extra patterning challenges to achieve high density. The two memory types are compared in terms of minimum area and critical design rules in both the iN10 and iN7 node, with an extra focus on patterning options in iN7. Both the use of Self-Aligned Quadruple Patterning (SAQP) mandrel and spacer engineering, as well as multi-level via’s are explored. These patterning options result in large area gains for the STT-MRAM cell and moreover determine which cell variant is the smallest.

The initial readiness of EUV patterning was demonstrated in 2016 with IBM Alliance's 7nm device technology. The focus has now shifted to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. Thus, Design Technology Co-optimization (DTCO) has become a critical part of technology enablement as scaling has become more challenging and the industry pushes the limits of EUV lithography. The working partnership between the design teams and the process development teams typically involves an iterative approach to evaluate the manufacturability of proposed designs, subsequent modifications to those designs and finally a design manual for the technology. While this approach has served the industry well for many generations, the challenges at the Beyond 7nm node require a more efficient approach. In this work, we describe the use of “Design Intent” lithographic layout optimization where we remove the iterative component of DTCO and replace it with an optimization that achieves both a “patterning friendly” design and minimizes the well-known EUV stochastic effects. Solved together, this “design intent” approach can more quickly achieve superior lithographic results while still meeting the original device’s functional specifications.

Specifically, in this work we will demonstrate “design intent” optimization for critical BEOL layers using design tolerance bands to guide the source mask co-optimization. The design tolerance bands can be either supplied as part of the original design or derived from some basic rules. Additionally, the EUV stochastic behavior is mitigated by enhancing the image log slope (ILS) for specific key features as part of the overall optimization. We will show the benefit of the “design intent approach” on both bidirectional and unidirectional 28nm min pitch standard logic layouts and compare the more typical iterative SMO approach. Thus demonstrating the benefit of allowing the design to float within the specified range. Lastly, we discuss how the evolution of this approach could lead to layout optimization based entirely on some minimal set of functional requirements and process constraints.

We demonstrate a tool which can function as an interface between VLSI designers and process-technology engineers throughout the Design-Technology Co-optimization (DTCO) process. This tool uses a Monte Carlo algorithm on the output of lithography simulations to model the frequency of fail mechanisms on wafer. Fail mechanisms are defined according to process integration flow: by Boolean operations and measurements between original and derived shapes. Another feature of this design rule optimization methodology is the use of a Markov-Chain-based algorithm to perform a sensitivity analysis, the output of which may be used by process engineers to target key process-induced variabilities for improvement. This tool is used to analyze multiple Middle-Of-Line fail mechanisms in a 10nm inverter design and identify key process assumptions that will most strongly affect the yield of the structures. This tool and the underlying algorithm are also shown to be scalable to arbitrarily complex geometries in three dimensions. Such a characteristic which is becoming more important with the introduction of novel patterning technologies and more complex 3-D on-wafer structures.

Conventional via patterning which relies on immersion ArF (iArF) lithography and self-aligned via (SAV) becomes challenging in sub-7nm technology. EUV lithography (EUVL) is expected to achieve smaller feature patterning thanks to its short wave length, but edge placement error (EPE) margin remains as another bottleneck of pitch scaling; SAV can be aligned with metal on the top but not with the bottom of the via. Literary study shows previous work on 2D self-aligned via (2D SAV) which can be aligned with the both metals, but it cannot extend technology scaling beyond sub-5nm whose minimum metal pitch is expected as sub-20nm due to essential limitation of EPE margin. We propose large marginal 2D SAV which has three times large EPE margin than normal 2D SAV for extremely shrunk technology node (e.g. sub-5nm). Large marginal 2D SAV may allow further feature size scaling, but it requires four EUV masks. Therefore, we present two count reduction methods and corresponding mask decompositions and pattern re-targetings. Proposed re-targeted patterns are assessed by source mask optimization (SMO) in terms of maximum EPE and process variation band (PVB) width.

Bidirectional cell refers to a standard cell, in which metal-1 is used for both horizontal and vertical connections. Unidirectional cell, on the other hand, assumes reserved routing, e.g. metal-1 for only horizontal and metal-2 for only vertical connections. It has been introduced to take advantage of regular metal patterns, which are easier to print and can overcome the lithography limitations in sub-32nm technology. In unidirectional cell, metal-2 is laid out following the cell placement pitch. Since metal-2 pitch is usually different from placement pitch, some within-cell metal-2 become off track. This significantly degrades metal-2 routability. We propose a unidirectional cell with floating metal-2. After initial cell placement, metal-2 segment within each cell is snapped to nearest metal-2 track and is fixed. In addition, we propose cell redesign and post-placement optimization to enhance metal-1 routability. Metal-1 connections are forced to populate in limited number of tracks, so that remaining tracks are exposed during routing. Combined with post-placement optimization, this allows many longer metal-1 tracks to be available for horizontal connection. Experiments with test circuits show that routing errors are reduced by 7% and 60% with the proposed metal-1 considerations and floating metal-2 together.

Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for mask end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer’s process margin is shrinking at advanced nodes to a point that classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on sub-resolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. To overcome the limitation of 1D metrics, there are numerous on-going industry efforts to better define wafer-predictive metrics through both standard mask metrology and aerial CD methods. Even with these improvements, the industry continues to struggle to define useful correlative metrics that link the mask to final device performance. In part 1 of this work, we utilized advanced mask pattern characterization techniques to extract potential hot spots on the mask and link them, theoretically, to issues with final wafer performance. In this paper, part 2, we complete the work by verifying these techniques at wafer level. The test vehicle (TV) that was used for hot spot detection on the mask in part 1 will be used to expose wafers. The results will be used to verify the mask-level predictions. Finally, wafer performance with predicted and verified mask/wafer condition will be shown as the result of advanced mask characterization. The goal is to maximize mask end user yield through mask-wafer technology harmonization. This harmonization will provide the necessary feedback to determine optimum design, mask specifications, and mask-making conditions for optimal wafer process margin.

High-throughput electron-beam lithography (EBL) by character projection (CP) and variable-shaped beam (VSB) methods is a promising technique for low-to-medium volume device fabrication with regularly arranged layouts, such as standard-cell logics and memory arrays. However, non-VLSI applications like MEMS and MOEMS may not fully utilize the benefits of CP method due to their wide variety of layout figures including curved and oblique edges. In addition, the stepwise shapes that appear on such irregular edges by VSB exposure often result in intolerable edge roughness, which may degrade performances of the fabricated devices. In our former study, we proposed a general EBL methodology for such applications utilizing a combination of CP and VSB methods, and demonstrated its capabilities in electron beam (EB) shot reduction and edge-quality improvement by using a leading-edge EB exposure tool, ADVANTEST F7000S-VD02, and high-resolution Hydrogen Silsesquioxane resist. Both scanning electron microscope and atomic force microscope observations were used to analyze quality of the resist edge profiles to determine the influence of the control parameters used in the exposure-data preparation process. In this study, we carried out detailed analysis of the captured edge profiles utilizing Fourier analysis, and successfully distinguish the systematic undulation by the exposed CP character profiles from random roughness components. Such capability of precise edge-roughness analysis is useful to our EBL methodology to maintain both the line-edge quality and the exposure throughput by optimizing the control parameters in the layout data conversion.

In nano-meter scale Integrated Circuits, via fails due to random defects is a well-known yield detractor, and via redundancy insertion is a common method to help enhance semiconductors yield. For the case of Self Aligned Double Patterning (SADP), which might require unidirectional design layers as in the case of some advanced technology nodes, the conventional methods of inserting redundant vias don’t work any longer. This is because adding redundant vias conventionally requires adding metal shapes in the non-preferred direction, which will violate the SADP design constraints in that case. Therefore, such metal layers fabricated using unidirectional SADP require an alternative method for providing the needed redundancy.

This paper proposes a post-layout Design for Manufacturability (DFM) redundancy insertion method tailored for the design requirements introduced by unidirectional metal layers. The proposed method adds redundant wires in the preferred direction - after searching for nearby vacant routing tracks - in order to provide redundant paths for electrical signals. This method opportunistically adds robustness against failures due to silicon defects without impacting area or incurring new design rule violations. Implementation details of this redundancy insertion method will be explained in this paper.

One known challenge with similar DFM layout fixing methods is the possible introduction of undesired electrical impact, causing other unintentional failures in design functionality. In this paper, a study is presented to quantify the electrical impacts of such redundancy insertion scheme and to examine if that electrical impact can be tolerated. The paper will show results to evaluate DFM insertion rates and corresponding electrical impact for a given design utilization and maximum inserted wire length. Parasitic extraction and static timing analysis results will be presented. A typical digital design implemented using GLOBALFOUNDRIES 7nm technology is used for demonstration.

The provided results can help evaluate such extensive DFM insertion method from an electrical standpoint. Furthermore, the results could provide guidance on how to implement the proposed method of adding electrical redundancy such that intolerable electrical impacts could be avoided.

Airgap refers to a void formed in place of some inter metal dielectric (IMD). It brings about the reduction in coupling capacitance, which may contribute to improvement in circuit performance. We introduce two problems in this context. First is to choose the layers, where airgap should be applied, in such a way that total negative slack (TNS) is minimized for a given circuit. This has been motivated by the fact that best choice of airgap layers is different for different circuits. An algorithm is proposed to solve the problem, and is assessed against a naive approach in which airgap layers are simply fixed; additional 8% TNS reduction, on average of a few test circuits, is demonstrated. In the second problem, some wires of critical paths that are on non-airgap layers are reassigned to airgap layers such that TNS is further reduced; additional 3 to 14% of TNS reduction is observed.

Line and cut based patterning for BEOL layers is an attractive solution to address the block mask patterning challenges related to self-aligned double patterning. It also enables integrated fill, with fill as an artifact of unused metal routes following lines and cuts patterning. Traditional post-layout fill involves inserting metal at large distances to limit design impact, but is less effective at alleviating metal thickness variation due to density effects. While integrated fill reduces metal thickness variation, it has a negative impact on capacitance, delay and power dissipation. This work studies the impact of pure lines/cuts integrated fill on design performance metrics using a predictive 7 nm PDK.

Two fully implemented auto-place and routed (APR) designs are considered for the experiments, one small and one large. Our comparison is from no fill to integrated fill, assuming conventional fill would not impact timing. The impact of integrated fill on capacitance and overall timing is evaluated using Calibre PEX and PrimeTime. We show these results are in line with simple “back of the envelope” estimates and simple models and are very significant for large designs.

As process technology scales down, the number of Chemical Mechanical Polishing (CMP) processes and steps used in chip manufacturing are increasing exponentially. Shrinking process margins increase the risk of excessive metal or oxide thickness or topography variations, causing potential yield problems such as dishing, erosion, resist lifting or printability issues.

Present DFM CMP modeling and applications mainly focus on the hotspot detection and fixing methodology for the Back-End-Of-Line (BEOL) layers ^[1]. Today, the present methodology is no longer sufficient to eliminate all the CMP related manufacturing defects. There is a strong demand for STI, poly and contact silicon calibrated CMP models to predict and fix the related CMP hotspots.

Shallow Trench Isolation (STI) and Poly CMP planarity is very critical in advanced technologies with Diffusion layer FIN structures and Replacement Metal Gate Process flow ^[2]. Gate uniformity after CMP will improve device performance, reduce CMP defects and increases the yield. Contact (Tungsten) CMP polishing is another important step that defines contact planarity, which will influence metal layer CMP planarization ^[3].

This paper will discuss design dependent CMP variations for STI, Poly and Contact CMP steps and showcase the importance of FEOL CMP modeling. We present the methodology for Silicon calibrated STI CMP, Poly and Contact CMP models and the applications of FEOL CMP models in CMP dishing and erosion hotspot analysis. We also present FEOL plus BEOL multi stack CMP simulations applications and provide design guidelines to fix CMP hotspots.

Lithographic patterning limits can be a cost-barrier that delays advancement to new nodes. This paper introduces a cost-saving design method that enables a maskless via. Multi-patterning or coloring of a design is a technique that is used at advanced nodes to aid in patterning. Coloring allows designers to designate different patterns on one level to be printed with different masks. Stitch overlap via (SOV) is a coloring technique introduced herein. SOV utilizes via-aware coloring and a unique process flow to print a maskless via. Identification of qualifying design structures is achieved through a custom program. The program inputs the design level of the multipatterned layer and the via levels above and below to determine the coloring decomposition. Vias are a particularly challenging layer to print due to the dimensions required for these pillars. SOV is a methodology for identifying qualifying multi-patterned layouts and replacing them with a new design that enables a maskless via layer.

Due to limited availability of DRC clean patterns during the process and RET recipe development, OPC recipes are not tested with high pattern coverage. Various kinds of pattern can help OPC engineer to detect sensitive patterns to lithographic effects. Random pattern generation is needed to secure robust OPC recipe. However, simple random patterns without considering real product layout style can’t cover patterning hotspot in production levels. It is not effective to use them for OPC optimization thus it is important to generate random patterns similar to real product patterns. This paper presents a strategy for generating random patterns based on design architecture information and preventing hotspot in early process development stage through a tool called Layout Schema Generator (LSG). Using LSG, we generate standard cell based on random patterns reflecting real design cell structure – fin pitch, gate pitch and cell height. The output standard cells from LSG are applied to an analysis methodology to assess their hotspot severity by assigning a score according to their optical image parameters - NILS, MEEF, %PV band and thus potential hotspots can be defined by determining their ranking. This flow is demonstrated on Samsung 7nm technology optimizing OPC recipe and early enough in the process avoiding using problematic patterns.

This research considers problem of sampling design space of a given physical design layout. More specifically, it deals with extraction of a set of characteristic design patterns evenly distributed within design space occupied by the layout. The methodology reported here is capable of condensing large design layouts comprised of billions of patterns to few tens of representative cases fulfilling needs of process development and process monitoring in a semiconductor manufacturing facility as well as for OPC and process compensation setup. Patterns extracted by this method include both patterns having high representation in the incoming design and anomalous configurations. In the case study we have sampled design space of a 22FDX test chip with 40 mm² area on a contact layer. Incoming design layout comprised of 763.6 million patterns has been condensed to 61 patterns that contained all anticipated design configurations as well as a couple of unexpected findings. Extractions of compact pattern representations and multi-step hierarchical clustering method enabling full chip execution (10⁶-10¹⁰ patterns) are discussed here in detail.

In advanced technology nodes, lithography hotspot detection has become one of the most significant issues in design for manufacturability. Recently, machine learning based lithography hotspot detection has been widely investigated, but it has trade-off between detection accuracy and false alarm. To apply machine learning based technique to the physical verification phase, designers require minimizing undetected hotspots to avoid yield degradation. They also need a ranking of similar known patterns with a detected hotspot to prioritize layout pattern to be corrected. To achieve high detection accuracy and to prioritize detected hotspots, we propose a novel lithography hotspot detection method using Delaunay triangulation and graph kernel based machine learning. Delaunay triangulation extracts features of hotspot patterns where polygons locate irregularly and closely one another, and graph kernel expresses inner structure of graphs. Additionally, our method provides similarity between two patterns and creates a list of similar training patterns with a detected hotspot. Experiments results on ICCAD 2012 benchmarks show that our method achieves high accuracy with allowable range of false alarm. We also show the ranking of the similar known patterns with a detected hotspot.

imec’s DTCO and EUV achievement toward imec 7nm (iN7) technology node which is industry 5nm node equivalent is reported with a focus on cost and scaling. Patterning-aware design methodology supports both iArF multiple patterning and EUV under one compliant design rule. FinFET device with contacted poly pitch of 42nm and metal pitch of 32nm with 7.5-track, 6.5-track, and 6-track standard cell library are explored. Scaling boosters are used to provide additional scaling and die cost benefit while lessening pitch shrink burden, and it makes EUV insertion more affordable. EUV pattern fidelity is optimized through OPC, SMO, M3D, mask sizing and SRAF. Processed wafers were characterized and edge-placement-error (EPE) variability is validated for EUV insertion. Scale-ability and cost of ownership of EUV patterning in aligned with iN7 standard cell design, integration and patterning specification are discussed.

Silicon testing results are regularly collected for a particular lot of wafers to study yield loss from test result diagnostics. Product engineers will analyze the diagnostic results and perform a number of physical failure analyses to detect systematic defects which cause yield loss for these sets of wafers in order to feedback the information to process engineers for process improvements. Most of time, the systematic defects that are detected are major issues or just one of the causes for the overall yield loss.

This paper will present a working flow for using design analysis techniques combined with diagnostic methods to systematically transform silicon testing information into physical layout information. A new set of the testing results are received from a new lot of wafers for the same product. We can then correlate all the diagnostic results from different periods of time to check which blocks or nets have been highlighted or stop occurring on the failure reports in order to monitor process changes which impact the yield. The design characteristic analysis flow is also implemented to find 1) the block connections on a design that have failed electrical test or 2) frequently used cells that been highlighted multiple times.

The IC chip manufacturing process is an integrated working flow where after each manufacturing step, a yield inspection team will apply great effort and machine resources to inspect and sort through various check points to detect silicon failures. However, despite the great effort, they cannot efficiently cover a whole chip and cross check all the different layers and products at the same time.

This paper will present a smart and efficient working flow that can map inspection data back onto a design and produce more diverse monitor points for inspection, and each set of monitor points links to a set of statistical design data that shows insight on design structures that are more sensitive to the process variations. A full-chip post-processing flow is also implemented to process design layout so that the particular patterns that may cause certain function blocks to fail can be directly checked on post-processed layout.

In this paper, standard cell design for iN7 CMOS platform technology targeting the tightest contacted poly pitch (CPP) of 42 nm and a metal pitch of 32 nm in the FinFET technology is presented. Three standard cell architectures for iN7, a 7.5-Track library, 6.5-Track library, and 6-Track library have been designed. Scaling boosters are introduced for the libraries progressively: first an extra MOL layer to enable an efficient layout of the three libraries starting with 7.5-Track library; second, fully self aligned gate contact is introduced for 6.5 and 6-Track library and third, 6-Track cell design includes a buried rail track for supply. The 6-Track cells are on average 5% and 45% smaller than the 6.5 and 7.5-Track cells, respectively.

In this paper, we describe an integrated design space analysis approach consisting of full factorial layout generation, lithography simulations with added proximity effects, and rigorous statistical analysis through monte-carlo simulations which is used in the evaluating interconnects. This agile Design rule development process provides a quick turnaround time to down-select the potential layout configurations that can offer a competitive, robust and reliable design and manufacturing. Further layout and placement optimization is carried out to evaluate intra-cell, inter-cell and cell boundary situations, which are critical for a place and routed block. These interconnects developed using the integrated approach has been the key contributor to give 20-30% higher performance at the same Iddq leakage for 8T libraries compared to Single Diffusion break or Double Diffusion break based 12T libraries in 22FDX Technology.

Since chip performance and power are highly dependent on the operating voltage, the robust power distribution network (PDN) is of utmost importance in designs to provide with the reliable voltage without voltage (IR)-drop. However, rapid increase of parasitic resistance and capacitance (RC) in interconnects makes IR-drop much worse with technology scaling. This paper shows various IR-drop analyses in sub 10nm designs. The major objectives are to validate standard cell architectures, where different sizes of power/ground and metal tracks are validated, and to validate PDN architecture, where types of power hook-up approaches are evaluated with IR-drop calculation. To estimate IR-drops in 10nm and below technologies, we first prepare physically routed designs given standard cell libraries, where we use open RISC RTL, synthesize the CPU, and apply placement & routing with process-design kits (PDK). Then, static and dynamic IR-drop flows are set up with commercial tools. Using the IR-drop flow, we compare standard cell architectures, and analysis impacts on performance, power, and area (PPA) with the previous technology-node designs. With this IR-drop flow, we can optimize the best PDN structure against IR-drops as well as types of standard cell library.

As technology advances, the need for running lithographic (litho) checking for early detection of hotspots before tapeout has become essential. This process is important at all levels—from designing standard cells and small blocks to large intellectual property (IP) and full chip layouts. Litho simulation provides high accuracy for detecting printability issues due to problematic geometries, but it has the disadvantage of slow performance on large designs and blocks [1]. Foundries have found a good compromise solution for running litho simulation on full chips by filtering out potential candidate hotspot patterns using pattern matching (PM), and then performing simulation on the matched locations. The challenge has always been how to easily create a PM library of candidate patterns that provides both comprehensive coverage for litho problems and fast runtime performance. This paper presents a new strategy for generating candidate real design patterns through a random generation approach using a layout schema generator (LSG) utility. The output patterns from the LSG are simulated, and then classified by a scoring mechanism that categorizes patterns according to the severity of the hotspots, probability of their presence in the design, and the likelihood of the pattern causing a hotspot. The scoring output helps to filter out the yield problematic patterns that should be removed from any standard cell design, and also to define potential problematic patterns that must be simulated within a bigger context to decide whether or not they represent an actual hotspot. This flow is demonstrated on SMIC 14nm technology, creating a candidate hotspot pattern library that can be used in full chip simulation with very high coverage and robust performance.

In order to allow competitive and low-cost designs in the 22nm FD-SOI technology 22FDX™, novel Middle-of-Line (MOL) constructs have been specifically enabled. The Gate Tie-Down (or “continuous RX”) construct allows an optimal device performance without loss of area. A method for a silicon-based evaluation and optimization of the Gate Tie-Down construct is presented here. We discuss the main design-process failure modes, their severity and the risk mitigation options. A full-factorial Design of Experiment used for the construct validation is presented and analyzed. Two critical failure modes are isolated and discussed. As a final step, the optimized design is validated over a much larger number of occurrences, showing a robust 4-sigma manufacturing design margin.

Current patterning technology for manufacturing memory devices is being developed towards enabling high density and high resolution capability. However, as applying high resolution technology results in decreased process margin, OPC has to compensate for such effect. Since the process margin is decreased greatly for contact layers, technologies such as RBAF (Rule-Based Assist Feature), MBAF (Model-Based Assist Feature), and ILT (Inverse Lithography Technology) are considered to maximize the process margin [1, 2, 3]. Although ILT is the best solution in terms of process margin, it has several disadvantages such as long OPC run-time, mask complexity, and unstable mask fidelity. MBAF method is a good compromise for more advanced techniques mitigating those risks (but not eliminating it), which is why it is often used for contact layers.

When setting up the rules for RBAF, not all patterns are considered. Thus, applying RBAF for contact layers may result in decreased process margin for certain patterns since the same rule is applied globally. MBAF, on the other hand, can maximize the process margin for various patterns as it generates AF (Assist Feature) to locations that maximize the margin for the patterns considered. However, MBAF method is very sensitive to even a slight change of a target, which influences the locations of the AF. This leads to generating different OPCed CD of the main features, even for those that should not be affected by the changed target. Once the OPCed CD is changed, it is impossible to obtain the same mask CD even when the mask is manufactured with the same method. If this case occurs during mass production, the entire layer needs to be confirmed after each revision which leads to unnecessary time loss.

In this paper, we suggest a new OPC method to prevent this issue. With this flow, OPCed shapes of unchanged patterns remain the same while only the changed targets are OPCed and replaced into the corresponding location, while the boundaries between those regions are corrected using a model based boundary healing. This method can reduce the overall OPCTAT as well as the time spent in verifying the entire layout after each revision. Details of these results will be described in this paper. After further studies, this flow can also be applied to ILT.

Analog circuits are sensitives to the changes in the layout environment conditions, manufacturing processes, and variations. This paper presents analog verification flow with five types of analogfocused layout constraint checks to assist engineers in identifying any potential device mismatch and layout drawing mistakes. Compared to several solutions, our approach only requires layout design, which is sufficient to recognize all the matched devices. Our approach simplifies the data preparation and allows seamless integration into the layout environment with minimum disruption to the custom layout flow. Our user-friendly analog verification flow provides the engineer with more confident with their layouts quality.

Beyond 40 nm technology node, the pattern weak points and hotspot types increase dramatically. The typical patterns for lithography verification suffers huge turn-around-time (TAT) to handle the design complexity. Therefore, in order to speed up process development and increase pattern variety, accurate design guideline and realistic design combinations are required. This paper presented a flow for creating a cell-based layout, a lite realistic design, to early identify problematic patterns which will negatively affect the yield.

A new random layout generating method, Design Technology Co-Optimization Pattern Generator (DTCO-PG), is reported in this paper to create cell-based design. DTCO-PG also includes how to characterize the randomness and fuzziness, so that it is able to build up the machine learning scheme which model could be trained by previous results, and then it generates patterns never seen in a lite design. This methodology not only increases pattern diversity but also finds out potential hotspot preliminarily.

This paper also demonstrates an integrated flow from DTCO pattern generation to layout modification. Optical Proximity Correction, OPC and lithographic simulation is then applied to DTCO-PG design database to detect hotspots and then hotspots or weak points can be automatically fixed through the procedure or handled manually. This flow benefits the process evolution to have a faster development cycle time, more complexity pattern design, higher probability to find out potential hotspots in early stage, and a more holistic yield ramping operation.

In advanced technology nodes, layout regularity has become a mandatory prerequisite to create robust designs less sensitive to variations in manufacturing process in order to improve yield and minimizing electrical variability. In this paper we describe a method for designing regular full custom layouts based on design and process co-optimization. The method includes various design rule checks that can be used on-the-fly during leaf-cell layout development. We extract a Layout Regularity Index (LRI) from the layouts based on the jogs, alignments and pitches used in the design for any given metal layer. Regularity Index of a layout is the direct indicator of manufacturing yield and is used to compare the relative health of different layout blocks in terms of process friendliness. The method has been deployed for 28nm and 40nm technology nodes for Memory IP and is being extended to other IPs (IO, standard-cell). We have quantified the gain of layout regularity with the deployed method on printability and electrical characteristics by process-variation (PV) band simulation analysis and have achieved up-to 5nm reduction in PV band.

This paper proposes a novel hotspots fixing flow, in which design rule optimization and lithography RET solution are obtained simultaneously. This flow is most effective in the early development phase, and its methodology is rooted from design technology co-optimization (DTCO). Two layout files, corresponding to separate colors of a double-pattern layer (10nm node M1), are first generated by a pattern generator, and they meet no-stitching requirements and are design rule check (DRC) clean. Then, source, mask and design rule co-optimization is done with the layouts, and the design rules are optimized to remove hotspots and enable maximum lithography process window (PW). The mask optimization (MO) in combination with cost function manipulation and design rule optimization improve the robustness of initial design rule. The application of the methodology illustrates a friendly design rule and avoids later design rework.

As the technology continues to shrink below 20nm, Double Patterning Technology (DPT) becomes one of the mandatory solutions for routing metal layers. From the view point of Place and Route (P&R), the major concerns are how to prevent DPT odd-cycles automatically without sacrificing chip area. Even though the leading-edge P&R tools have advanced algorithms to prevent DPT odd-cycles, it is very hard to prevent the localized DPT odd-cycles, especially in Engineering Change Order (ECO) routing. In the last several years, we developed In-design DPT Auto Fixing method in order to reduce localized DPT odd-cycles significantly during ECO and could achieve remarkable design Turn-Around Times (TATs). But subsequently, as the design complexity continued increasing and chip size continued decreasing, we needed a new In-design DPT Auto Fixing approach to improve the auto. fixing rate.

In this paper, we present the Stitching-Aware In-design DPT Auto Fixing method for better fixing rates and smaller chip design. The previous In-design DPT Auto Fixing method detected all DPT odd-cycles and tried to remove oddcycles by increasing the adjacent space. As the metal congestions increase in the newer technology nodes, the older Auto Fixing method has limitations to increase the adjacent space between routing metals. Consequently, the auto fixing rate of older method gets worse with the introduction of the smaller design rules. With DPT stitching enablement at In-design DRC checking procedure, the new Stitching-Aware DPT Auto Fixing method detects the most critical odd-cycles and revolve the odd-cycles automatically. The accuracy of new flow ensures better usage of space in the congested areas, and helps design more smaller chips.

By applying the Stitching-Aware DPT Auto Fixing method to sub-20nm logic devices, we can confirm that the auto fixing rate is improved by ~2X compared with auto fixing without stitching. Additionally, by developing the better heuristic algorithm and flow for DPT stitching, we can get DPT compliant layout with the acceptable design TATs.

Foundries normally receive a large number of designs from different customers every day. It is desired to automatically profile each incoming design to quantify certain metrics like 1) the number of polygons per GDS layers 2) what kind of electrical components the design contains 3) what the dimensions of each electrical component are 4) how frequently any size of components have been used and their physical locations.

This paper will present a novel method of how to generate a complete profile of components for any particular design. The component checking flow need to be completed within hours so it will have very little impact on the tape-out time. A pre-layer checking method is also run to group commonly used layers for different electrical components and then employ different layout profiling flows. The foundry does this design chip analysis in order to find potentially weak devices due to their size or special size requirements for particular electrical components. The foundry can then take pre-emptive action to avoid yield loss or make an unnecessary mask for new incoming products before fab processing starts.

As feature sizes and pitches continue to decrease, more complex correction algorithms are needed to solve increasingly difficult geometric configurations. Usage of these more complex algorithms results in unacceptably long time-to-mask when applied to an entire design. In many cases, the more complex algorithms are only required in a small percentage of areas of the entire design, and these areas are not always known prior to tapeout. Hotspot fixing (HSF) flows are increasingly used to fix these hotspot areas to minimize errors and decrease time-to-mask. These flows involve “recorrecting” a design, using the previous correction output as the input to the HSF flow. This input file contains a hierarchy that was optimized for the original correction. Hotspot areas are frequently smaller than the original correction areas and frequently repeat in unique cell outputs of the original correction, so the optimal hierarchy for a HSF fix flow may be very different from the original correction. A new hierarchy, optimized for HSF, is difficult to form from the corrected output. This paper describes the usage of pattern-matching to regain hierarchical compression for identical hotspot areas that are not repeating cells in the original correction. Using this pattern-matching HSF flow, turnaround time for the hotspot fixing can be more than 50X faster than re-using the original correction’s hierarchy for complex HSF methods. These significant gains can be achieved in spite of the additional complexity it can add to the flow. In the case where simpler/faster HSF correction methods are used, significant turnaround time gains can still be made by using this pattern matching technique.

Hotspot fixing methodologies are increasingly deployed during tapeouts as a means to optimize the tradeoffs between complex, highly accurate correction methods and faster methods that are sufficient for most pattern areas.¹ However, pattern database hierarchies may not be optimum for these hotspot fixing flows, as they are optimized for the initial correction run or method. This paper examines the usage of pattern matching to regain hierarchy and significantly reduce turn-around-time for complex hotspot fixing methods. Gains in turn-around-time can be well over 50 times faster than reusing the original correction’s hierarchy.

As technology advances, IC designs are getting more sophisticated, thus it becomes more critical and challenging to fix printability issues in the design flow. Running lithography checks before tapeout is now mandatory for designers, which creates a need for more advanced and easy-to-use techniques for fixing hotspots found after lithographic simulation without creating a new design rule checking (DRC) violation or generating a new hotspot. This paper presents a new methodology for fixing hotspots on layouts while using the same engine currently used to detect the hotspots. The fix is achieved by applying minimum movement of edges causing the hotspot, with consideration of DRC constraints. The fix is internally simulated by the lithographic simulation engine to verify that the hotspot is eliminated and that no new hotspot is generated by the new edge locations. Hotspot fix checking is enhanced by adding DRC checks to the litho-friendly design (LFD) rule file to guarantee that any fix options that violate DRC checks are removed from the output hint file. This extra checking eliminates the need to re-run both DRC and LFD checks to ensure the change successfully fixed the hotspot, which saves time and simplifies the designer’s workflow. This methodology is demonstrated on industrial designs, where the fixing rate of single and dual layer hotspots is reported.

Systematic yield detractors are normally expected to be identified by ATPG test result diagnostics. Different test patterns have been designed to test different functions. Test diagnostics can identify failed functions so that product engineers, based on testing results, can narrow down which block in the design performs this function. However, it is often hard to narrow down to a more specific region in a product.

This paper will present a working flow for using design diffing techniques to extract layout structures and perform a geometry analysis flow combined with testing results to find most probable suspects that may cause noticeable yield loss.

It is very well known that as technology nodes move to smaller sizes, the number of design rules increases while design structures become more regular and the process manufacturing steps have increased as well. Normal inspection tools can only monitor hard failures on a single layer. For electrical failures that happen due to inter layers misalignments, we can only detect them through testing.

This paper will present a working flow for using pattern analysis interlayer profiling techniques to turn multiple layer physical info into group linked parameter values. Using this data analysis flow combined with an electrical model allows us to find critical regions on a layout for yield learning.

There is an increasing demand for device level layout analysis, especially as technology advances. The analysis is to study standard cells by extracting and classifying critical dimension parameters. There are couples of parameters to extract, like channel width, length, gate to active distance, and active to adjacent active distance, etc. for 14nm technology, there are some other parameters that are cared about. On the one hand, these parameters are very important for studying standard cell structures and spice model development with the goal of improving standard cell manufacturing yield and optimizing circuit performance; on the other hand, a full chip device statistics analysis can provide useful information to diagnose the yield issue. Device analysis is essential for standard cell customization and enhancements and manufacturability failure diagnosis. Traditional parasitic parameters extraction tool like Calibre xRC is powerful but it is not sufficient for this device level layout analysis application as engineers would like to review, classify and filter out the data more easily. This paper presents a fast and efficient method based on Calibre equation-based DRC (eqDRC). Equation-based DRC extends the traditional DRC technology to provide a flexible programmable modeling engine which allows the end user to define grouped multi-dimensional feature measurements using flexible mathematical expressions. This paper demonstrates how such an engine and its programming language can be used to implement critical device parameter extraction. The device parameters are extracted and stored in a DFM database which can be processed by Calibre YieldServer. YieldServer is data processing software that lets engineers query, manipulate, modify, and create data in a DFM database. These parameters, known as properties in eqDRC language, can be annotated back to the layout for easily review. Calibre DesignRev can create a HTML formatted report of the results displayed in Calibre RVE which makes it easy to share results among groups. This method has been proven and used in SMIC PDE team and SPICE team.

Pattern-based approaches are becoming more common and popular as the industry moves to advanced technology nodes. At the beginning of a new technology node, a library of process weak point patterns for physical and electrical verification are starting to build up and used to prevent known hotspots from re-occurring on new designs. Then the pattern set is expanded to create test keys for process development in order to verify the manufacturing capability and precheck new tape-out designs for any potential yield detractors. With the database growing, the adoption of pattern-based approaches has expanded from design flows to technology development and then needed for mass-production purposes. This paper will present the complete downstream working flows of a design pattern database(PDB). This pattern-based data analysis flow covers different applications across different functional teams from generating enhancement kits to improving design manufacturability, populating new testing design data based on previous-learning, generating analysis data to improve mass-production efficiency and manufacturing equipment in-line control to check machine status consistency across different fab sites.

We demonstrate two different approaches of implementing design technology co-optimization (DTCO). One is on optimizing standard cells. Before being placed on mask, standard cells can be evaluated and optimized to gain better process windows. This approach enables an additional learning cycle before mask tapeout, reducing process development cost. The other approach uses a random pattern generator to create various patterns with high coverage based on given design rules. Lithography simulation is used to evaluate process window of these patterns, and annotates its printability. Test patterns generated in this way can be used for early process development.