This PDF file contains the front matter associated with SPIE Proceedings Volume 10284, including the Title Page, Copyright information, Table of Contents, and Conference Committee listing.

Vertical-cavity surface-emitting lasers have emerged as viable optical sources for lowpower, low-cost interconnects. Work over the past few years has involved the use of several different structures, including etched-mesa, proton-implanted and dielectric apertured types. Although much of the development work aimed at manufacture has focused on the proton-implanted structure, more recent work suggests that lower threshold, higher-efficiency configurations may be more desirable for future applications. In this review, we briefly outline the different structures, introduce a general design formalism, overview growth and fabrication issues, summarize some integration work, and finally review some applications that have been identified. Free-space interconnects with AlGaAs/GaAs-based materials will be emphasized including a brief summary of recent work on links using integrated microlenses on the VCSELs and detectors to avoid external optics. For completeness, we shall also include some discussion of the progress in long-wavelength InP-based (1.3 - 1.55 μm) and short-wavelength AlInGaP/GaAsbased (0.8 - 0.6 μm) VCSELs as well as guided-wave data links.

Future advances in the application of photonic interconnects will involve the insertion of parallel-channel links into Multi-Chip Modules (MCMs) and board-level parallel connections. Such applications will drive photonic link components into more compact forms that consume far less power than traditional telecommunication data links. These will make use of new device-level technologies such as vertical cavity surfaceemitting lasers and special low-power parallel photoreceiver circuits. Depending on the application, these device technologies will often be monolithically integrated to reduce the amount of board or module real estate required by the photonics. Highly parallel MCM and board-level applications will also require simplified drive circuitry, lower cost, and higher reliability than has been demonstrated in photonic and optoelectronic technologies. An example is found in two-dimensional point-to-point array interconnects for MCM stacking. These interconnects are based on high-efficiency Vertical Cavity Surface Emitting Lasers (VCSELs), Heterojunction Bipolar Transistor (HBT) photoreceivers, integrated micro-optics, and MCM-compatible packaging techniques. Individual channels have been demonstrated at 100 Mb/s, operating with a direct 3.3V CMOS electronic interface while using 45 mW of electrical power. These results demonstrate how optoelectronic device technologies can be optimized for low-power parallel link applications.

This paper presents the concepts of a board-to-board free space optical interconnection scheme that will support a bus architecture. While the technology required to implement this optical scheme is very compatible with existing electronic packaging technologies, it promises to be able interconnect many more boards together without serious impedance matching or termination problems encountered by electrical interconnects at high speed. Experimental demonstration of the optical scheme is in progress.

Free-space optical interconnects are an attractive method for providing data channels between the chips in a multichip module because free-space optical interconnects offer the promise of lower energy, higher bandwidth data pathways than are possible with electronics. In this paper, we describe the range of operating conditions in which free-space optical interconnects offer a performance improvement over conventional electronic interconnects and over other optical interconnection techniques. The high performance optoelectronic computing (HPOC) module architecture is suitable for chip-to-chip communications in a multichip module. We show that, in addition to simply transferring data between chips or performing clock distribution, the HPOC module architecture can be used to perform calculations. It is necessary to modify the optical design of the HPOC module to make it conform to the coplanar geometry of the multichip module. An estimate is made of the performance capabilities of the HPOC module for data pipeline, clock distribution, and data routing in multichip modules. Finally, we show that multichip modules equipped with optical interconnects can be used for switching and data routing applications.

Diffraction from multi-level phase holograms can be used to implement completely general free-space optical interconnect patterns. This paper provides a review of the basic forward problem of diffraction from a multi-level phase structure, the inverse problem of designing a computer-generated hologram to achieve a specific interconnect, and the issues involved in the performance analysis of these interconnect holograms.

The various optical interconnection schemes that have been developed for the implementation of neural network architectures are reviewed. Volume holography in photorefra.ct.ive crystals is the most powerful interconnection method for this application. The use of liquid crystal smart pixel technology for the realization of the nonlinear activation function of the neurons is described. A novel method for combining liquid crystal devices and photorefractive holograms that leads to a very compact and versatile package, is presented.

We propose a new method for implementing a large optoelectronic (O-E) crossbar interconnect switch [1], Based on an emerging vertical-cavity surface-emitting laser (VCSEL) technology, a passive angle-multiplexed beam steering architecture is proposed as a key component of the O-E crossbar. Various optical system parameters are evaluated. Since there is no optical fan-out power loss, the interconnect capacity of the proposed system is determined by the diffraction-limited receiver power cut-off and therefore interconnection of more than 1,000 nodes with a per node bandwidth of 1 GHz using today's technology is possible.

System architectures for optoelectronic parallel computing system are reviewed and a massively parallel processing system with a reconfigurable optical interconnection among electronic general purpose processing elements (PE’s) is described as an example. If PE is so compact, more than 4,000 PE’s can be integrated into one chip for directly coupling with array type optical devices in parallel. The optical interconnection is constructed using a surface emitting laser diode array and a phase modulation type spatial light modulator on which optimized computer generated holograms are written. In this paper, the design concept of optoelectronic parallel computing systems and PE’s, configurations of experimental system, and algorithms for parallel optoelectronic computing system are shown.

In this paper we review network related performance issues for current Massively Parallel Processors (MPPs) in the context of some important basic operations in scientific and engineering computation. The communication system is one of the most performance critical architectural components of MPPs. In particular, understanding the demand posed by collective communication is critical in architectural design and system software implementation. We discuss collective communication and some implementation techniques therefore on electronic networks. Finally, we give an example of a novel general routing technique that exhibits good scalability, efficiency and simplicity in electronic networks.

Optics will soon established as the mainstay for data-intensive communications at distances about 100 meters or less between workstations, displays and peripherals. The datacom hardware includes of arrays of multi-mode vertical-cavity surface-emitting lasers (VCSELs) emitting in the 650-1000 nm range and parallel channels of multi-mode optical fiber, which are major departures from the already-established long-distance optical fiber communications for telecom. These radical departures are brought about by two major forces. (1) They are forced by the driving need to reduce costs for datacom links to the consumer affordability level, as opposed to the network provider level in telecom links. (2) They are allowed by the different requirements of the shorter communication distances. In the future, optics is expected to replace traditional communication links at even shorter distances. If optical communications extends down to the inter-chip level, it is likely that the “chipcom” links will require technologies as different from datacom technologies as VCSEL arrays and fiber ribbons are from distributed feedback lasers and single-mode fibers. In this paper are reviewed the forces which shape the emerging datacom hardware, current state of datacom links, and a cmde forecast of what will be required for chipcom links.

In the implementation of optical data links, issues of power consumption, bandwidth and sensitivity have to be addressed in the design of optoelectronic components. This is especially important in high density parallel applications where large amount of heat can cause thermal management problem and performance degradation. We present low-power, low-cost, short wavelength (850 nm) GaAs MSM/MESFET (Metal-Semiconductor-Metal / Metal Semiconductor Field Effect Transistor) monolithic OptoElectronic Integrated Circuit (OEIC) receiver arrays which were designed, fabricated, and tested at the University of Illinois at Urbana-Champaign (UIUC). Four-channel OEIC receiver arrays with a BER of less than 10^-9 have been measured at 1 Gb/s with a -16 dBm 2⁷-1 Pseudo-Random Bit Sequence (PRBS) input optical signal. The sensitivity was -20 dBm (BER = 10^-9. The development of a lower power version by the Vitesse/MOSIS 0.6 μm E/D-MESFET technology is also presented. Four channel OEIC receivers and several single channel OEIC receivers were developed in the Vitesse Semiconductor Corporation HGaAsIII process by the UIUC. The designs were completed at the UIUC and submitted to MOSIS for fabrication in the HGaAsIII process. Good results have been obtained. The single stage amplifier configuration's average measured performance parameters are: 52.5 dB-Ω gain, 1.4 GHz bandwidth, 76 mW DC power consumption, and 127 V/W responsivity (calculated). The two stage amplifier configuration's average measured performance parameters are: 81.5 dB-Ω gain, 825 MHz bandwidth, 150 mW DC power consumption (estimated), and 3.6 kV/W responsivity (calculated). The three stage amplifier configuration's average estimated performance parameters are: 111 dB-Ω gain, 485 MHz bandwidth, 170 mW DC power consumption, and 106 kV/W responsivity. The four stage amplifier amplifier's average estimated performance parameters are: 139 dB-Ω gain, 285 MHz bandwidth, 190 mW power consumption, and 1.5 MV/W.

This paper reviews recent results for clock recovery circuits operating at speeds in excess of 1 Gbit/sec or realized as multichannel arrays. The emphasis is on Synchronous Optical NETwork (SONET) type systems, their requirements, and the effect of the clock recovery circuits on system performance. Clock recovery approaches include filter based, phase-lockcd-loops, and all-optical methods.

We review the recent results on the design and implementation of the performance-optimized bidirectional optical backplane bus aimed at high speed multiprocessor systems. It employs an array of multiplexed holograms, in conjunction with a waveguiding plate within which cascaded fanouts are generated. Data transfer rate of 1.2 Gbit/sec at 1300 nm is demonstrated with a single bus line for a system composed of nine boards. Packaging-related issues and misalignment effects are addressed. Theoretical treatment to minimize fluctuations among the received powers at each board was carried out and the overall performance was optimized. We also introduce a hybrid optical backplane with multiple bus lines. The hybrid backplane maintains the same waveguiding structure, and exploits optoelectronic array devices. A new demonstration system is being implemented. The optical backplane that we developed is transparent to higher level bus protocols, thus can support standard backplane buses such as Futurebus+, Multibus II, and VMEbus.

Several interconnect Junctions within cabinets comprising high performance computers are pushing the limits of electrical interconnect technology. A widespread problem of limited interconnect density at the board-to-backplane interface has been identified, while advances in clock speed and cabinet functionality are expected to stress electrical interconnects first for high fanout applications, then for high speed point-to-point parallel interconnects. Key components are described, and from these components the design of a generic optical backplane technology is described. While components are now available to implement a practical solution, the use of proven electrical techniques is considered an important step in hastening the introduction of the technology.

We have developed a parallel processor system with 152 RISC processor chips specific for Monte-Carlo analysis. This system has the ring-bus architecture. The performance of several Gflops is expected in this system according to the computer simulation. However, it was revealed that the data transfer speed of the bus has to be increased more dramatically in order to further increase the performance. Then, we propose to introduce the optical interconnection into the parallel processor system to increase the data transfer speed of the buses. The double ringbus architecture is employed in this new parallel processor system with optical interconnection. The free-space optical interconnection arid the optical waveguide are used for the optical ring-bus. Thin polyimide film was used to form the optical waveguide. A relatively low propagation loss was achieved in the polyimide optical waveguide. In addition, it was confirmed that the propagation direction of signal light can be easily changed by using a micro-mirror.

Optical interconnects are used in Cray Research Incorporated supercomputers for both clock distribution and channel communications. Currently, we are developing a new inter cabinet communications channel called GigaRing™ that will incorporate photonic components to meet channel bandwidth-distance requirements. Both commercially available and experimental serial optic data links, as well as parallel optic data links have been examined. After briefly describing the channel’s architecture, we present a comparison study showing the cost, performance and reliability results between serial and parallel data link components that could be used in the optical extension of the channel. With these comparison results, it is demonstrated that the serial data links best meet the channel’s requirements at present.

Wafer and chip stacking are envisioned as means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper will provide definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies will be discussed.

The Parallel Optical Link Organization (POLO) is an ARPA sponsored industry consortium consisting of four companies and one university. The members are Hewlett- Packard, AMP, Du Pont, SDL, and the University of Southern California. The consortium’s goal is to develop a high speed (1 Gbyte/s) parallel optical interconnect module for applications in central office switching environments and clustered computing. Previous reports1 have described the general layout of the POLO interconnect module and reported preliminary results. In this paper, we discuss further progress to date on the POLO module and show results for a 10 channel module operating at 622 Mb/s per channel. In addition, we discuss the current performance limitations of the module, packaging issues associated with assembly, a testbed which utilizes the POLO interconnect for the transmission of high resolution images between workstations, and plans for the 2nd generation POLO module.

The Polymer Optical Interconnect Technology (POINT) represents a major collaborative effort among GE, Honeywell, AMP, AlliedSignal, Columbia University and the University of California at San Diego (UCSD), sponsored by ARPA, in developing affordable optoelectronic module packaging and interconnect technologies for board- and backplane- level optical interconnect applications for a wide range of military and commercial applications. The POINT program takes a novel development approach by fully leveraging the existing electronic design, processing, fabrication and module packaging technologies to optoelectronic module packaging. The POINT program further incorporates several state-of-the-art optoelectronic technologies that include high-speed VCSEL for multichannel array data TM transmission; flexible optical polymers such as Polyguide or coupling of device-to-fiber using a passively alignment process; a low-loss polymer for backplane interconnect to provide a high I/O density; low-cost diffractive optical elements (DOE) for board-to-backplane interconnect; and use of molded MT array ferrule to reduce overall system size, weight, and cost. In addition to further reducing design and fabrication cycle times, computer simulation tools for optical waveguide and mechanical modeling will be advanced under the POINT program.

Free space optical interconnect phase holograms fabricated in poly-methyl methacrylate films by direct-write electron beam lithography have been characterized both physically and optically. Performance of holograms containing common fabrication errors is simulated using both Fourier optics and, for a simple one dimensional hologram, a numerical solution of the Helmholtz equation. The degradation of optical performance due to measured fabrication errors and design errors is discussed in view of the simulation results.

Planar polymer waveguide technologies have shown the promise for applications in multi-port modulation and switching systems. We describe a key application of electro-optic polymer waveguides to modulator arrays and then illustrate the state-of-the-art performance obtained with our lxN thermo-optic switches.

LIGA is a fabrication technology suitable for mass producing high aspect-ratio microstructured components with nearly arbitrary 3D shapes in almost any material. The acronym stems from the German words for lithography, electroforming, and plastic molding. Fabricating highly parallel microoptical systems either for guided-wave or for free-space light transmission by LIGA technology may turn out to be a cost-effective way to satisfy optical interconnect demands.

This paper describes a new interconnect and local area network transmission concept for computer communications based on spectrally encoding one or more computer words into a wavelength datagram. At physical and data link level, this system resembles an optical ribbon cable, except that all the bits pass on one fiber optic waveguide. At the network level, such fiber optic link segments can be interconnected all-optically using 2x2 optical switches into ShuffleNet or other architectures that permit a photonic packet to pass from source to destination without being incumbered with the extra delay and bandlimiting associated with electronic switching and regeneration. Unique properties of such a system include low latency (<10ns), very high bandwidth (<100Gbit/s per port), precise time alignment (<10ps) of the individual word bits over km distances, and dynamic scalability to support cluster computing and distributed supercomputing. Novel system elements disclosed in this paper include: (J) a bit parallel wavelength (BPW) fiber optic link that uniquely maintains wavelength channel time alignment, (2) an innovative parallel stepped wavelength optical transmitter that time synchronizes each laser diode element at its optical output, (3) a spectral encoder/decoder that adds fault tolerance and optical message addressing capability, and (4) a technique for transmitting and maintaining time aligned multi-X solitons as parallel bits through fiber media. Applications to teraflop high performance parallel computing and DoD input/output (I/O) bound applications are described.