Encoding of chain outputs in FPGA-based Moore FSMs

Alexander Barkalov; Larysa Titarenko; Jacek Bieganowski

doi:10.1117/12.2281060

7 August 2017 Encoding of chain outputs in FPGA-based Moore FSMs

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski

Proceedings Volume 10445, Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments 2017; 104452N (2017) https://doi.org/10.1117/12.2281060
Event: Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2017, 2017, Wilga, Poland

Abstract

A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with FPGAs. The method is based on replacement of the state register by a state counter. The specific of the proposed method is that the counter content is incremented for unconditional and conditional transitions. An example of application of proposed method is given.

Citation Download Citation

Alexander Barkalov, Larysa Titarenko, and Jacek Bieganowski "Encoding of chain outputs in FPGA-based Moore FSMs", Proc. SPIE 10445, Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments 2017, 104452N (7 August 2017); https://doi.org/10.1117/12.2281060

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