This PDF file contains the front matter associated with SPIE Proceedings Volume 10446, including the Title Page, Copyright information, Table of Contents, Foreword, and Conference Committee listing.

At TNO an extensive EUV optics life time program has been running for over 15 years together with our partners ASML and Carl Zeiss. This has contributed to the upcoming introduction of EUV High Volume Manufacturing (HVM). To further help the industry with the introduction of EUV, TNO has worked on extending their facilities with a number of reticle and pellicle research infrastructure facilities. In this paper we will show some of the facilities that are available at TNO and shortly introduce their capabilities. Recently we have opened our EBL2 facility, which is an EUV Beam Line (EBL2) meant for studying the effects of high power EUV illumination on optics, reticles and pellicles up to the power roadmap of 500 W at intermediate Focus (IF). This facility is open to users from all over the world and is beneficial for the industry in helping developing alternative capping layers and contamination control strategies for optics lifetime, new absorber materials, pellicles and resists. The EBL2 system has seen first light in December 2016 and is now in the final stage of acceptance testing and qualification. It is expected that the system will be fully operational in the third quarter of 2017, and available for users. It is possible to transfer reticles to and from the EBL2 by means of the reticle handler using the dual pod interface. This secures backside cleanliness to NXE standards and thus enables wafer printing on a NXE tool in a later stage after the exposures and inspection at EBL2. Besides EBL2, a high performance and ultra-clean reticle handler is available at TNO. This handler incorporates our particle scanner Rapid Nano 4 for front side inspection of reticle blanks with a detection limit down to 20 nm particles. Attached to the handler is also an Optical Coherence Tomography (OCT) inspection tool for back-side reticle or pellicle inspection with a resolution down to 1 micron.

The 5nm and 7nm technology nodes will continue recent scaling trends and will deliver significantly smaller minimum features, standard cell areas and SRAM cell areas vs. the 10nm node. There are tremendous economic pressures to shrink each subsequent technology, though in a cost-effective and performance enhancing manner. IC manufacturers are eagerly awaiting EUV so that they can more aggressively shrink their technology than they could by using complicated MPT. The current 0.33NA EUV tools and processes also have their patterning limitations. EUV scanner lenses, scanner sources, masks and resists are all relatively immature compared to the current lithography manufacturing baseline of 193i. For example, lens aberrations are currently several times larger (as a function of wavelength) in EUV scanners than for 193i scanners. Robustly patterning 16nm L/S fully random logic metal patterns and 40nm pitch random logic rectangular contacts with 0.33NA EUV are tough challenges that will benefit from advanced OPC/RET. For example, if an IC manufacturer can push single exposure device layer resolution 10% tighter using improved ILT to avoid using DPT, there will be a significant cost and process complexity benefit to doing so. ILT is well known to have considerable benefits in finding flexible 193i mask pattern solutions to improve process window, improve 2D CD control, improve resolution in low K1 lithography regime and help to delay the introduction of DPT. However, ILT has not previously been applied to EUV lithography. In this paper, we report on new developments which extend ILT method to EUV lithography and we characterize the benefits seen vs. traditional EUV OPC/RET methods.

With the introduction of the NXE:3400B EUV scanner, ASML brings to the market the next generation NXE system. In this paper we present the results of a subset of a larger investigation that aimed at assessing the imaging performance of the NXE:3400B in various scenarios. The use cases we chose for the presentation here are contact holes, which are typical building blocks for logic and memory applications. In this paper we evaluate typical lithographic metrics. Starting from the exposure latitude, we show that contact holes of already 17nm half-pitch can be printed. Next, we show that the full wafer CD uniformity improvement is mainly driven by a high reticle CD uniformity. After that, we explore the capabilities of the new NXE:3400B illuminator and investigate an improved illumination setting for relaxed staggered contact holes of half pitch >21nm, and show a 20% local CD uniformity improvement (from 4.6 to 3.6nm) for regular contact holes of 18nm half-pitch, without throughput loss.

Multi-beam mask writer MBM-1000 will be released in Q4 2017 for N5 semiconductor production. The motivation to go to multi-beam is high throughput at aggressive shot count. MBM-1000 performs better than EBM-9500, which is our latest VSB writer, at shot count of 500 G/pass or more because of exposure count and beam current independent to figure count. Key technology for high throughput is cathode and high-voltage power supply which provides large beam emission current, inline data path and blanking aperture array (BAA) with 300 Gbps data ratio. In this paper, design of data path and BAA for MBM-1000 are described.

Irresistible Materials is developing a new molecular resist system that demonstrates high-resolution capability based on the Multi-trigger concept. In a Multi-Trigger resist, multiple distinct chemical reactions in chemical amplification process must take place in close proximity simultaneously during resist exposure. Thus, at the edge of a pattern feature, where the density of photo-initiators that drive the chemical reactions is low, the amplification process ceases. This significantly reduces blurring effects and enables much improved resolution and line edge roughness while maintaining the sensitivity advantages of chemical amplification. A series of studies such as enhanced resist crosslinking, elimination of the nucleophilic quencher and the addition of high-Z additives to e-beam resist (as a means to increase sensitivity and modify secondary electron blur) were conducted in order to optimize the performance of this material. The optimized conditions allowed patterning down to 28 nm pitch lines with a dose of 248 μC/cm² using 100kV e-beam lithography, demonstrating the potential of the concept. Furthermore, it was possible to pattern 26 nm diameter pillars on a 60 nm pitch with dose of 221μC/cm² with a line edge roughness of 2.3 nm.

The application of EUV lithography at the 7 nm node and below requires, among others, to reduce 3D mask effects¹ like shadowing e.g. by introducing a thinner absorber structure. A search for new potential absorber materials with improved optical properties is done within the ECSEL JU project SeNaTe^2,3,4,5. The standard Ta-based absorber system of the actual photomasks has been optically characterized in detail as the benchmark. The results are in agreement with the optical data presently used in the optical modeling of EUV photomasks. As candidates for an alternative absorber material, Ni, Co, NiAl are investigated. For the investigation of the alternative EUV mask absorber materials, metal layers of several 10 nm were deposited on silicon wafers. At PTB the spectral reflectance was measured in the angular range from normal incidence to grazing incidence in a wavelength band from 10 nm to 16 nm using PTB’s lubricationfree Ellipso-Scatterometer at the soft X-ray radiometry beamline. The measured reflectance is then fitted using Fresnel’s equations to a layer model accounting for thickness and roughness of the metal layer and additional top-oxide and a SiO₂ layer on the Si-substrate surface. We present here an update on the optical constants of Ni, Co and NiAl layers.

This paper describes the use of model-based MPC in mask manufacturing for the 14 nm technology node and beyond, analyzes the requirements and challenges for introducing MPC and highlights its benefits in the mask manufacturing process.

Multibeam electron beam systems will be used in the future for mask writing and for complimentary lithography. The major challenges of the multibeam systems are in meeting throughput requirements and in handling the large data volumes associated with writing grayscale data on the wafer. In terms of future communications and computational requirements Amdahl’s Law suggests that a simple increase of computation power and parallelism may not be a sustainable solution. We propose a parallel data compression algorithm to exploit the sparsity of mask data and a grayscale video-like representation of data. To improve the communication and computational efficiency of these systems at the write time we propose an alternate datapath architecture partly motivated by multibeam direct write lithography and partly motivated by the circuit testing literature, where parallel decompression reduces clock cycles. We explain a deflection plate architecture inspired by NuFlare Technology’s multibeam mask writing system and how our datapath architecture can be easily added to it to improve performance.

Currently, flat panel displays (FPDs) are one of the main parts for information technology devices and sets. From 1990's to 2000's, liquid crystal displays (LCDs) and plasma displays had been mainstream FPDs. In the middle of 2000's, demand of plasma displays declined and organic light emitting diodes (OLEDs) newly came into FPD market. And today, major technology of FPDs are LCDs and OLEDs. Especially for mobile devices, the penetration of OLEDs is remarkable. In FPDs panel production, photolithography is the key technology as same as LSI. Photomasks for FPDs are used not only as original master of circuit pattern, but also as a tool to form other functional structures of FPDs. Photomasks for FPDs are called as "Large Size Photomasks(LSPMs)", since the remarkable feature is " Size" which reaches over 1- meter square and over 100kg. In this report, we discuss three LSPMs technical topics with FPDs technical transition and trend. The first topics is upsizing of LSPMs, the second is the challenge for higher resolution patterning, and the last is “Multi-Tone Mask” for "Half -Tone Exposure".

In this paper key challenges posed on metrology by feature dimensions of 20nm and below are discussed. In detail, the need for software-based tools for SEM image acquisition and image analysis in environments where CD-SEMs are not available and/or not flexible enough to cover all inspection tasks is outlined. These environments include research at universities as well as industrial R and D environments focused on non-IC applications. The benefits of combining automated image acquisition and analysis with computational techniques to simulate image generation in a conventional analytical SEM with respect to the overall reliability, precision and speed of inspection will be demonstrated using real-life inspection tasks as demonstrators.

For defect disposition and repair verification regarding printability, AIMS™ is the state of the art measurement tool in industry. With its unique capability of capturing aerial images of photomasks it is the one method that comes closest to emulating the printing behaviour of a scanner. However for nanoimprint lithography (NIL) templates aerial images cannot be applied to evaluate the success of a repair process. Hence, for NIL defect dispositioning scanning, electron microscopy (SEM) imaging is the method of choice. In addition, it has been a standard imaging method for further root cause analysis of defects and defect review on optical photomasks which enables 2D or even 3D mask profiling at high resolutions. In recent years a trend observed in mask shops has been the automation of processes that traditionally were driven by operators. This of course has brought many advantages one of which is freeing cost intensive labour from conducting repetitive and tedious work. Furthermore, it reduces variability in processes due to different operator skill and experience levels which at the end contributes to eliminating the human factor. Taking these factors into consideration, one of the software based solutions available under the FAVOR® brand to support customer needs is the aerial image evaluation software, AIMS™ AutoAnalysis (AAA). It provides fully automated analysis of AIMS™ images and runs in parallel to measurements. This is enabled by its direct connection and communication with the AIMS™tools. As one of many positive outcomes, generating automated result reports is facilitated, standardizing the mask manufacturing workflow. Today, AAA has been successfully introduced into production at multiple customers and is supporting the workflow as described above. These trends indeed have triggered the demand for similar automation with respect to SEM measurements leading to the development of SEM AutoAnalysis (SAA). It aims towards a fully automated SEM image evaluation process utilizing a completely different algorithm due to the different nature of SEM images and aerial images. Both AAA and SAA are the building blocks towards an image evaluation suite in the mask shop industry.

We present nanostructured reflectors as alternative for well-known alternating layer stack reflectors for Fabry-Pérot Interferometers (FPI) for the use in miniaturized spectrometry systems. The addressed FPI is part of an online monitoring system for specific molecules by Surface Enhanced Raman Spectroscopy (SERS). Key part is the tunable FPI with nanostructured reflectors, which is fabricated with MEMS and NEMS technologies. Nanostructured Photonic Crystal (PhC) and Sub-Wavelength Grating (SWG) reflectors are developed. The PhC reflectors consisting of 400 nm thin moveable LP-CVD Si₃N₄ membranes with nanostructured holes realize an aperture of 1 mm with high reflectivity in the VIS range. The SWG reflectors are realized as nanostructured aluminum polygons on 150 nm thin LP-CVD Si₃N₄ membranes. The challenge in manufacturing of the PhC and SWG structures on 50 μm thin predefined silicon membrane areas is the thin wafer handling, because they are very fragile and tend to warp under their own weight. Further challenges such as delamination of the NIL-stamp from the wafer and eBeam resist homogeneity on the deflected thin silicon membranes for nanostructure replication as well as residual free resist layers for the followed RIE process and the match of the used Nanoimprint, 1:1 and eBeam lithography processes for the different layers have to be considered. The manufacturing and characterization of both alternative reflectors for prospective integration in VIS-FPIs on 6" wafers is described.

Line Edge Roughness is largely used in the current semiconductor research and industry for the evaluation of materials and processes since it is considered one of the critical factors to degrade device performance. Therefore, its accurate measurement and complete characterization though complicated is highly required. LER measurement is usually based on the analysis of top-down SEM images. As a result, it suffers from the limitations of image-based metrology which among others are the presence of noise and the digital nature of images. Recently, several studies have paid attention on the impact of image noise on LER metrics and the aliasing effects on the Power Spectrum Density curves caused by the discreteness of edge data along line/edge direction. However, image digitization imposes discretization of edge data also in the vertical to edge/line direction. In this paper, we focus on the effects of this aspect of edge data discretization on LER rms value and PSD curve. We explain and analyze the effect using synthesized SEM images and identify the critical role of the ratio of rms to pixel size. We find that for such ratios larger than 0.6, the image digitization has a fixed contribution to the measured rms roughness and PSD which should be removed to mitigate these effects.

Today’s technology nodes contain more and more complex designs bringing increasing challenges to chip manufacturing process steps. It is necessary to have an efficient metrology to assess process variability of these complex patterns and thus extract relevant data to generate process aware design rules and to improve OPC models. Today process variability is mostly addressed through the analysis of in-line monitoring features which are often designed to support robust measurements and as a consequence are not always very representative of critical design rules. CD-SEM is the main CD metrology technique used in chip manufacturing process but it is challenged when it comes to measure metrics like tip to tip, tip to line, areas or necking in high quantity and with robustness. CD-SEM images contain a lot of information that is not always used in metrology. Suppliers have provided tools that allow engineers to extract the SEM contours of their features and to convert them into a GDS. Contours can be seen as the signature of the shape as it contains all the dimensional data. Thus the methodology is to use the CD-SEM to take high quality images then generate SEM contours and create a data base out of them. Contours are used to feed an offline metrology tool that will process them to extract different metrics. It was shown in two previous papers that it is possible to perform complex measurements on hotspots at different process steps (lithography, etch, copper CMP) by using SEM contours with an in-house offline metrology tool. In the current paper, the methodology presented previously will be expanded to improve its robustness and combined with the use of phylogeny to classify the SEM images according to their geometrical proximities.

Traditional CD-SEM metrology reaches its limits when measuring complex configurations (e.g. advanced node contact configurations). SEM extracted contours embody valuable information which is essential for building a robust etch prediction model ^{[1, 2].} CDSEM recipe complexity, processing time and measurement robustness can be improved using contour based metrology. However, challenges for measurement pattern selection as well as final model verification arise. In this work, we present the full flow of implementing etch prediction models calibrated and verified with SEM contours into a manufacturing environment.

As the concepts of machine learning and artificial intelligence continue to grow in importance in the context of internet related applications it is still in its infancy when it comes to process control within the semiconductor industry. Especially the branch of mask manufacturing presents a challenge to the concepts of machine learning since the business process intrinsically induces pronounced product variability on the background of small plate numbers. In this paper we present the architectural set up of a machine learning algorithm which successfully deals with the demands and pitfalls of mask manufacturing. A detailed motivation of this basic set up followed by an analysis of its statistical properties is given. The machine learning set up for mask manufacturing involves two learning steps: an initial step which identifies and classifies the basic global CD patterns of a process. These results form the basis for the extraction of an optimized training set via balanced sampling. A second learning step uses this training set to obtain the local as well as global CD relationships induced by the manufacturing process. Using two production motivated examples we show how this approach is flexible and powerful enough to deal with the exacting demands of mask manufacturing. In one example we show how dedicated covariates can be used in conjunction with increased spatial resolution of the CD map model in order to deal with pathological CD effects at the mask boundary. The other example shows how the model set up enables strategies for dealing tool specific CD signature differences. In this case the balanced sampling enables a process control scheme which allows usage of the full tool park within the specified tight tolerance budget. Overall, this paper shows that the current rapid developments off the machine learning algorithms can be successfully used within the context of semiconductor manufacturing.

Process optimization depends largely on field engineer’s knowledge and expertise. However, this practice turns out to be less sustainable due to the fab complexity which is continuously increasing in order to support the extreme miniaturization of Integrated Circuits. On the one hand, process optimization and root cause analysis of tools is necessary for a smooth fab operation. On the other hand, the growth in number of wafer processing steps is adding a considerable new source of noise which may have a significant impact at the nanometer scale. This paper explores the ability of historical process data and Machine Learning to support field engineers in production analysis and monitoring. We implement an automated workflow in order to analyze a large volume of information, and build a predictive model of overlay variation. The proposed workflow addresses significant problems that are typical in fab production, like missing measurements, small number of samples, confounding effects due to heterogeneity of data, and subpopulation effects. We evaluate the proposed workflow on a real usecase and we show that it is able to predict overlay excursions observed in Integrated Circuits manufacturing. The chosen design focuses on linear and interpretable models of the wafer history, which highlight the process steps that are causing defective products. This is a fundamental feature for diagnostics, as it supports process engineers in the continuous improvement of the production line.

In the last decades the semiconductor technology has been driven by Moore’s law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP’s 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA’s into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of ±500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP’s 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.

For certain designs, we observe a rather peculiar defect during phase-shift mask production. At distinct positions on the mask, the chrome disappears within the second level process in almost perfect half circles. This effect can even be observed if no etching is applied at all. The root cause of this defect is electrochemical dissolving of chrome in DI water during the development rinse process, which appears at locations where the chrome is in contact to the developer rinse medium. In this publication we describe the experimental set-up to investigate the root cause mechanism and propose solutions to overcome the effect.

Using the electron beam (e-beam) as an advanced metrology tool in semiconductor manufacturing technologies has attracted many interests in the recent years. Owing to its high resolution and transparency to a wide range of materials including the metals, the e-beam shows a great promise to be used individually or in combination with the current optical metrology techniques in semiconductor industries. However, the e-beam can cause damages to the materials under inspection due to its relatively high energy. Therefore, determining the amount and type of damage as a result of the e-beam exposure is critical. Here, we present scanning probe microscopy techniques with the capability of measuring the e-beam induced damages on various materials. The experimental results of the e-beam induced damages on 300 mm silicon wafers covered by 1) patterned low-k material and 2) patterned low-k material filled with copper metal after chemical-mechanical polishing treatment are discussed. This method can be considered as a complementary approach to e-beam to ensure minimizing damage to the features.

As nodes become smaller and smaller, the OPC applied to enable these nodes becomes more and more sophisticated. This trend peaks today in curve-linear OPC approaches that are currently starting to appear on the roadmap. With this sophistication of OPC, the mask pattern complexity increases. CD-SEM based mask qualification strategies as they are used today are starting to struggle to provide a precise forecast of the printing behavior of a mask on wafer. An aerial image CD measurement performed on ZEISS Wafer-Level CD system (WLCD) is a complementary approach to mask CD-SEMs to judge the lithographical performance of the mask and its critical production features. The advantage of the aerial image is that it includes all optical effects of the mask such as OPC, SRAF, 3D mask effects, once the image is taken under scanner equivalent illumination conditions. Additionally, it reduces the feature complexity and analyzes the printing relevant CD.

Authors of the report have been developing Sub-Wavelength Holographic Lithography (SWHL) methods of aerial image creation for IC layer topologies for the last several years. Sub-wavelength holographic masks (SWHM) have a number of substantial advantages in comparison with the traditional masks, which are used in projection photo-microlithography. The main advantages: there is no one-to-one correspondence between mask and image elements thus the effect of local mask defects almost completely eliminated [1]; holographic mask may consist of single-tipe elements with typical size many times bigger than projection mask elements [2]; technological methods of image quality optimization can be replaced by virtual routines in the process of the holographic mask calculating, that simplifies mask manufacturing and dramatically reduces the mask cost [3]; imaging via holographic mask does not need the projection lens, that significantly simplifies photolithographic tool and reduces ones cost. Our group developed effective methods of holographic mask synthesis and of aerial images modelling and created software package. This methods and calculation results were verified and reported many times [1-3].

We are investigating the possibilities and the technical requirements to do nanopatterning on arbitrary curved surfaces. This is done considering the opportunities and possibilities of additive manufacturing. One of the key elements is the necessity to deposit material in well-defined areas of various complex 3D objects. In order to achieve this we are developing a robot-based inkjet printing. We report on our progress with this respect and also on our efforts to perform nanoimprinting on curved, possibly 3D-printed objects using materials that can be deposited by inkjet printing. In the framework of this article, we provide an overview over our current status, the challenges and an outlook.

Successful patterning requires good control of the photolithography and etch processes. While compact litho models, mainly based on rigorous physics, can predict very well the contours printed in photoresist, pure empirical etch models are less accurate and more unstable. Compact etch models are based on geometrical kernels to compute the litho-etch biases that measure the distance between litho and etch contours. The definition of the kernels as well as the choice of calibration patterns is critical to get a robust etch model. This work proposes to define a set of independent and anisotropic etch kernels –“internal, external, curvature, Gaussian, z_profile” – designed to capture the finest details of the resist contours and represent precisely any etch bias. By evaluating the etch kernels on various structures it is possible to map their etch signatures in a multi-dimensional space and analyze them to find an optimal sampling of structures to train an etch model. The method was specifically applied to a contact layer containing many different geometries and was used to successfully select appropriate calibration structures. The proposed kernels evaluated on these structures were combined to train an etch model significantly better than the standard one. We also illustrate the usage of the specific kernel “z_profile” which adds a third dimension to the description of the resist profile.

We characterize the impact of high-energy, 172 nm vacuum ultraviolet photons on the molecular weight and the glass transition temperature of poly(methyl methacrylate). We found that the molecular weight is reduced strongly on the surface of the exposed samples with a continuous transition towards the unexposed bulk material being located below the modified region. The glass transition temperature was found to be significantly lowered in the exposed region to well below 50°C compared to that of the 122°C of the bulk region. We could use this material contrast to selectively reflow the top surface of the exposed samples only. This allowed us to create ultra-smooth micro-optical structures by post-processing without influencing the overall geometry that is required for the optical functionality.