This PDF file contains the front matter associated with SPIE Proceedings Volume 10959 including the Title Page, Copyright information, Table of Contents, Author and Conference Committee lists.

During the last several years we have seen an impressive drive in the industry to continue to innovate in order to keep up with the challenging requirements of overlay in multi-patterning processes. A major part of these efforts is spent in opening up of the flexibility in control knobs on process tools (mostly lithography and etch) enabling the high order actuation capability. In order to feed this high order actuation, it has also become important to address the need of input data accuracy, driving up the demand for improved metrology accuracy and sampling. Adding to the complexity, it has also become important to address edge placement error (EPE). EPE is basically the pattern fidelity of a device structure created by a multi-patterning process, defined as the relative displacement of the edges of two features from their intended target position. Here local CD error is an important parameter in addition to overlay. EPE requirements of a "single digit nanometer number" is now a harsh reality in 5nm nodes and below.

In this technical presentation we will review the above developments and remaining gaps in technology (litho and dimensional metrology applications), as well as design and integration. Mitigation of such challenges need a large team effort that is industry-wide and not just limited in litho.

Over the last 20 years there has been a steady increase in fundamental physics research and the hardware development needed to realize a quantum computer. However, in the last 5 years we have seen a dramatic increase in the interest from industry, including a variety of major semiconductor and technology leaders such as IBM, Google and Intel. This is the result of both a better understanding of the variety of problems that can be addressed and the impact that will come with quantum computing along with the emergence of a couple of potentially scalable hardware solutions. In a recent interview with a leading manufacturer, an aggressive strategy was laid out to achieve an operational 1000-qubit quantum computer within 5 years that can solve a variety of problems not addressable by conventional computing and the 10-year prospect to achieve a 1 million qubit machine that would “profoundly change society”. The major technology leaders view quantum information (QI) as a technology that they must begin to develop and understand today. Augmenting existing technology with QI is desirable, but , there are a variety of technical challenges to making silicon-based QI systems with the needed quantum properties and coherence times. New challenges in atomic precision and individual atom or electron effects that fundamentally affect device performance bring on a variety of new manufacturing and metrology challenges. Measuring electron spin coherence, exchange energies, and qubit fidelity are entirely new measurements for the semiconductor industry. Even the resolution of TEM may be inadequate, as TEM of a nominally 80 nm thick slice of silicon which averages many atoms together in a measurement where only one or two atoms can deeply change device performance, coherence times, or introduce charge offsets. After developing some of the first cold atom and ion trap quantum information demonstrations at NIST, we are now investing significantly in developing the supporting metrology and modeling methods needed to help industry develop and commercialize this new technology. In this presentation we will provide an overview of hardware solutions for quantum computing, future metrology needs and challenges to enable manufacturable quantum computers. Although industry leaders are now investing in superconducting qubits and silicon-based qubits, the two leading technologies, this talk will primarily focus on the principles of solid state silicon QI operation, manufacturing metrology solutions, and measurements needed to develop and evaluate viable technological solutions.

EUV lithography and multi patterning introduce variability often referred to as EUV and Etch stochastics. These consume a large part of the EPE (Edge Placement Error) budget. To bring EPE to the necessary specifications, the industry needs to minimize the key EPE contributors of CD, Overlay, pattern placement, pitch-walk, and LER. The challenge is that these attributes are being gauged by different metrology technologies, thus just matching these different metrology techniques might consume the entire EPE budget. Hence, the industry has sought solutions presented in this work that are capable of measuring the above attributes of EPE from a single image. The study presented will then investigate weather measuring all of EPE on a scribe like target introduces a pitch dependent bias that could be rid of - if all of EPE was measured on device. The paper will show data from thousands of EUV vias over multi-patterned interconnects of a real device. Once established that measuring on device is not prone to pitch dependent bias. The work will compare measuring and correcting EPE at ADI - after develop inspection, to reduce the time to accuracy compared to known methods of measuring accuracy, only at AEI, after etch. An attempt is made to investigate weather after etch accuracy methods used today insert a litho to etch metrology driven bias. After walking the audience through an EPE metrology budget minimization flow based on real images and data, the paper will look for further opportunities to minimize EPE at the source, such as self-aligned processes, beyond litho, specifically discussing spacer uniformity, and etch slant control versus overlay.

Metal containing resists (MCR) are one of the candidates for Extreme Ultraviolet (EUV) resists aiming to achieve the resolution, linewidth roughness and sensitivity (RLS) requirements of advanced design nodes. MCRs intrinsically have high etch resistance owing to their metal content. Therefore, low resist thickness (~18nm) is sufficient to transfer resist patterns into an underlying hard mask. Also, the thin resist reduces susceptibility to pattern collapse during development because of low aspect ratio. However, thus far little attention has been paid to optical metrology and inspectability (overlay, defect inspection, scatterometry, etc.) of these resists, which is another critical requirement to move MCR toward high volume manufacturing (HVM).

In this paper, we investigate overlay metrology and overlay correction with MCR. Even though the optical contrast for MCR is slightly lower than for chemically amplified resist (CAR) it seemed sufficient for high-quality overlay metrology. However, the measurement precision for MCR is deteriorated compared to that for CAR, resulting in significantly higher residuals. The root cause of the deteriorated measurement precision was found in grains in the optical image after MCR development. Interestingly, the after etch performance of CAR and MCR is identical. We demonstrate that with sufficient sampling, appropriate correctables can be extracted from the MCR overlay results. Finally, we discuss how the increased image noise can be compensated by the applied sampling scheme.

Shrinking on-product overlay (OPO) budgets in advanced technology nodes require more accurate overlay measurement and better measurement robustness to process variability. Pupil-based accuracy flags have been introduced to the scatterometry-based overlay (SCOL) system to evaluate the performance of a SCOL measurement setup. Wavelength Homing is a new robustness feature enabled by the continuous tunability of advanced SCOL systems using a supercontinuum laser light source in combination with a flexible bandpass filter. Inline process monitoring using accuracy flags allows for detection, quantification and correction of shifts in the optimal measurement wavelength. This work demonstrates the benefit of Wavelength Homing in overcoming overlay inaccuracy caused by process changes and restoring the OPO and residual levels in the original recipe.

In next generation 3D-NAND devices, accurately determining after-etch overlay for the multi-layer stack is a major challenge. This is especially the case for the multi-tier 3D-NAND structures, where the overlay of the channel holes is an important performance parameter. The most commonly used after-etch metrology suffer both from the high aspect ratio of the channel holes and from the potential presence of large tilts.

Using In-Device Metrology (IDM), we show results of non-destructive overlay measurements on 3D-NAND memory holes. Once the overlay signal has been determined, the remaining asymmetry information in the measurement can be used to characterize tilt phenomena densely through the memory array.

Using hyper-dense in-device measurements show the overlay effects of intra-die stress. A new lithography scanner model is used to correct specifically for such intra-die overlay fingerprints.

A standalone alignment technology was developed as a fundamental solution to improve on-product overlay (OPO). It enables high performance alignment measurements, and delivers state-of-the-art feed-forward corrections to exposure scanners. Dense alignment sampling and high order alignment correction is effective for scanner fingerprint matching and for correcting heavy distortion at a wafer edge. A mark asymmetry correction is detailed as effective solution which improves the OPO performance for heavily processed wafers. An OPO test result showed significant improvement using its feed-forward corrections. A high accuracy topography sensor is described as a new metrology innovation. The standalone alignment technology provides critical metrology tool functions such as process monitoring as well.

Voids in copper lines are a common failure mechanism in the back end of line (BEOL) of integrated circuits manufacturing, affecting chip yield and reliability. As subsequent process nodes continue to shrink metal line dimensions, monitoring and control of these voids gain more and more importance [1]. Currently, there is no quantitative in-line metrology technique that allows voids to be identified and measured. This work aims to develop a new method to do so, by combining scatterometry (also referred to as Optical Critical Dimension or Optical CD) and low-energy x-ray fluorescence (LE-XRF), as well as machine learning techniques. By combining the inputs from these tools in the form of hybrid metrology, as well as with the incorporation of machine learning methods, we create a new metric, referred to as V_xo, to characterize the quantity of void. Additionally, the results are compared with inline electrical test data, as higher amounts of voids were expected to increase the measured resistivity. This was not found to be the case, as the impact of the voids was much less of a factor than variation in the cross-sectional area of the lines.

Critical dimension scanning electron microscopes (CD-SEMs) are widely used as the tool for measuring the actual size, shape, and roughness of device patterns in the semiconductor manufacturing. In order to obtain an image with a high sig-nal-to-noise ratio (SNR), the usage of higher electron beam current or the averaging operation of scanning frames (long observation time) are carried out. Such methods, however, could increase the sample charging effects. In recent years, the application of deep learning to translation problems from images to images has attracted attention. Isola et al. have proposed the conditional generative adversarial networks (cGANs) as a general-purpose solution of trans-lation problems. The cGANs are shown in figure 1 [1]. The generative adversarial network (GAN), that has become the basis of the cGANs, consists of a generator G and a discriminator D. The generator G translates input images to plausible images. The discriminator D tries to distinguish real images from the image synthesized by the generator G while the gen-erator aims to generate plausible images as possible to fool the discriminator. Just as GANs, the cGANs learn a conditional generative model. This makes cGANs suitable for image-to-image translation task. For the generator, a “U-Net”-based architecture is used. For the discriminator, a convolutional “PatchGAN” classifier is used, which only penalizes structure at the scale of image patches. They have shown that this approach is effective on a wider range of problems. In this paper, we try to improve the quality (high resolution and high SNR) of a low-quality SEM image using the cGAN. In the training process, two kinds of images, low-quality images observed with low magnification and low SNR and corresponding high-quality images with high magnification and high SNR, are used. In the estimation process, an in-put low-quality SEM image is translated (outputted) to the high-quality image. Here we report the simulation results. Figure 2 shows a part of the training dataset that includes isolated single line. The high (upper row) and low (lower row) quality SEM images consist of 512 x 512 and 256 x 256 pixels, respectively. In the training, 3600 pairs (high and low) were used. Figure 3 shows an example of results. (a) is the low-quality input image, (b) the output image by the cGAN, and (c) the corresponding high-quality image (not used in the training). It is seen that the quality of the input image is improved to a degree close to the quality of the high-quality image while maintaining the outline of line edge roughness. [1] P. Isola, J.-Y. Zhu, T. Zhou, and A. A. Efros, arXiv preprint arXiv:1611.07004 (2016).

Metrology of most advanced CMOS devices poses more and more challenges: lithography and etch patterning processes need to be controlled on critical parameters that -beyond critical dimensions (CD)- nowadays also include line width and line edge roughness (LWR/LER), multiple patterning induced pitch-walk and, due to the high aspect ratio of the patterned structures, also thermo-mechanical structural bending.

In this paper, it is shown that sufficient sampling is required to ensure that scanning transmission electron microscopy (STEM) does provide relevant information about the dimensions and chemical composition of the advanced devices. While, in principle, STEM can measure device dimensions with Angstrom resolution and sub-nm precision, a single measurement will not be representative for the device dimensions that are known to vary statistically (LER/LWR) as well as systematically (Pitch-walk, structural bending).

In this context, the metrology capabilities of a (calibrated) automated 80-200kV STEM with Cs aberration corrector and a high efficiency EDS detector have been evaluated for both STEM-EDS and STEM-HAADF acquisitions. It will be shown that, when measuring multiple (~ 400) individual FinFET structures (Silicon Fins / dummy Silicon gate lines), average CD, LER and LWR can be quantified from the distribution of measured line widths and line pitches, that SADP and SAQP induced pitch-walk may show up as multi-modal pitch distributions, and that pitch walking can be quantified if also structural bending, that is observed, is properly taken into account.

Finally, the STEM and EDS metrology capabilities for FinFET and NanoWire (NW) device structures are reviewed for different use cases (statistical process control and technology development support) and with different indicators (Precision over Tolerance ratio (P/T) and Variability ratio (r = 1 – σ² _metrology / σ² _{measured process} )).

The control of edge placement error (EPE) is playing key role in the patterning of advanced technology node in semiconductor industry. EPE is evaluated by the metric of overlay, distance of patterns between two layers in multi patterning, and patterning error in local area. In past instance, overlay between upper layer and underlayer was measured by electron beam (e-beam) metrology system with scanning electron microscopy (SEM) image.

EPE which is caused by local patterning error on photoresist layer is influenced by scanner tool parameters such as focus and exposure. Technology and method of EPE measurement on photoresist layer is highly required to optimize scanner tool performance.

This study provides the measurement method of EPE on photoresist layer resulting from variation of scanner tool condition. Definition of EPE in this study is the distance between contour of SEM pattern and contour of target layout. Die to Database (D2DB) technology which compares image and layout data was applied to this study with large image size which include huge number of patterns. The advantage of the method was confirmed by the experiment on the verification of local patterning error.

The result of the experiment shows scanner tool conditions are well represented by these local patterning errors. In addition, optimizing scanner parameters and monitoring scanner condition by these local patterning errors are proposed.

Stochastic print failures are a serious potential yield limiter for the 5 nm and 3 nm technology node. To attain the detection limits that ensure yield requires inspection of square centimeters of area, which will challenge even the fastest anticipated e-beam tools. Optical techniques help but lack the ability to resolve actual defects. Applying super-resolution fluorescence nanoscopy techniques may provide a solution for both rapid inspection and defect identification capable of inspecting hundreds of wafers per hour. The technique first developed by Stephan Hell in 1994 for the life sciences uses the ability to toggle a molecules fluorescence on and off by activating with actinic light and deactivating via stimulated-depletion. By surrounding activating light with deactivating light, the former’s spot size reduces to nanometers allowing resolutions that far exceed the Abbe limit. In 2014, Professor Hell shared the Nobel Prize in chemistry for this technique, Stimulated-Emission-Depletion, STED nanoscopy. This paper will explain the technique, propose a method in its use for the inspection of EUV resists, and demonstrate proof-of-concept where we imaged with 775 nm deactivation and 640 nm activation morphological structures in a polymer film that are smaller than 5 nm.

With growing process complexity and the increasing number of process steps, early prediction of device performance has become an important task in semiconductor manufacturing process control. Machine learning (ML) techniques allow us to link in-line measurements to End-Of-Line (EOL) electrical tests. In our paper, we use reflectance spectra obtained from the scatterometry tool to predict both metal-line resistance and capacitance. We used IMEC N14 process flow with LELE double patterning at the M1 stage. Special designs-of-experiments (DOE) for multiple parameters allowed us to create a metrology solution for the entire process window and test its accuracy for all POI. Induced variations of both line CDs and space CDs, together with specially designed measurement sites, created wide variations both in metal-line resistance and capacitance. Reflectance spectra were collected in-line at two process steps defining metal lines: HM etch and Cu CMP at multiple targets, including E-test measurement sites, together with reference metrology for overlay (OV) and CD (by using Diffraction-Based-Overlay (DBO) and CD SEM). EOL electrical test results were used for the ML training procedure for early prediction of patterning effects (both CD and OL) on electrical performance enabling early decisions and cost reduction by discarding out-of-spec wafers before they reached the electrical test. It was shown that ML OCD predictive techniques are complimentary to the OCD model-based solutions for geometrical parameters widely used for in-line APC.

Full abstract not available at present - I will submit it this week or early next week.

Up until now, the main driving force for the semiconductor industry is the continual shrinkage of device feature sizes, thereby incorporating more devices per unit area, reducing manufacturing cost and enhancing their performance have been achieved. However, the shrinkage of feature size leads to a reduction of process window imposing an extremely tight requirement for parameters such as critical dimension (CD), edge and width roughness of spaces/trenches, contacts, lines, and tip to tip (T2T) values. At sub 14 nm technology nodes these parameters have a significant influence on the overall device performance. With EUV based pattering becoming the sole option at these advanced nodes, a thorough characterization of the patterning process is of utmost importance before it can be a high-volume manufacturing solution.

In this work, we show how e-beam inspection has been used to characterize a single exposure EUV M2 (Metal 2 layer, BEoL) to have an understanding of the different hotspots and intra-field signatures present. Design Based Metrology (DBM) with wide SEM image was employed to measure CD distribution and Edge Placement Error (EPE) distribution of metal layer pattern on the 10nm logic wafer.

Process monitoring of critical dimensions and structural shapes in 3D NAND flash memory device manufacturing requires the precision, resolution, and speed of SEM image acquisition and metrology, with new challenges in the Z axis, as device capacity continues to grow. Automated, gas assisted PFIB surface preparation enables sampling at multiple, arbitrary heights in the memory cell stack at a rate fast enough support inline process control. This work reports on preparation and measurement of greater than 2000 devices, from three sites, at 3 layers, in <140 minutes from a commercially available 64 layer 3D NAND device. Automated SEM metrology is used as a fast and accurate method of surface analysis to determine the planar cell area, ellipsis, and position of the bits as a function of depth within the stack. These results and extended analyses provide insight into how the shape and size of the primary etch channel influences memory cell dimensional variation as a function of depth.

Standard wafers with programmed defects (PDs) were fabricated to evaluate charge control techniques, resolution, and defect detection capabilities of pattern inspection tools for 7-nm and smaller nodes. To evaluate charge control techniques, the PDs were formed in line and space (LS) patterns. PDs were also formed below contact holes as programmed etching residues. These PDs were detected by a voltage contrast inspection technique. Image distortion by charging was also evaluated with the use of a wafer in a multibeam secondary electron microscope (SEM) and projection type inspection systems. Patterns with PDs were also formed on different subsurface structures. The effects of subsurface structures on the defect detection capability were evaluated based on this wafer. Another type of wafer having small defects approximately 5 nm in size on 16- to 12-nm half pitch (hp) LS patterns on a 12-inch Si-wafer, was fabricated by electron beam lithography. This wafer allowed evaluation of the defect detection capability of PDs having different shapes and sizes, such as protrusion, intrusion, bridge and open defects, on dense patterns for 7-nm and smaller nodes. Moreover, extremely small protrusion defects, with a size of 1 nm, and small bridge defects (as narrow as 1 nm) were also fabricated into LS patterns with ultra-low line-edge-roughness on a Si (110) substrate. This patterned substrate was mounted into a 12-inch Si wafer, and we evaluated the performance of tools for 12-inch wafer fabrication. We proposed a method to verify the true LER/LWR by CD-SEM measurements.

Even though instrumentation for electron beam lithography (EBL) has progressed immensely since it was first introduced almost 50 years ago[1], enabling beam spot sizes below 5 nm for certain systems, its lithographic resolution limits are still bound by the primary and secondary electron scattering processes that occur when a specific resist is exposed. As the feature sizes become smaller and resists designed with higher sensitivities, these stochastic processes play an increasing role in the resulting line edge roughness (LER) thus leading to an effect known as shot noise. Unfortunately, unraveling the impact of these processes from the impact of the development step is partly hindered by our inability to measure the 3D profile of the latent image from resists directly after exposure. Furthermore, given the recent rise of chemically-amplified resists (CARs) used for the next generation extreme ultraviolet lithography (EUV), it has become even more critical to find ways to characterize and investigate the shot noise effect. In this work, we tackle this challenge by applying the resonant soft x-ray scattering (RSoXS) technique in a grazing incidence configuration to extract the cross-sectional profile of resists that have already been patterned, but have yet to be developed (i.e., latent image). We find that the difference in chemistry induced by the chain scission process in exposed PMMA and CAR resists is enough to produce enough scattering contrast at certain X-ray energies near the absorption edge of carbon in order to provide a latent image profile of the pattern with sub-nanometer resolution. In this paper, we will compare the latent image profiles extracted from this RSoXS data to the profiles obtained after development, as well as expand on the nature of this chemical contrast mechanism. We will show how this scattering data may be interpreted and the information used to shed light on the nature of the resolution limit of a specific combination of resist and exposure plus development conditions. Finally, we will elaborate on the impact of the measurement itself on the resulting pattern morphology as well as how similar insights might be gained across other types of resists. 1. Hans C. Pfeiffer, } "Direct write electron beam lithography: a historical overview", Proc. SPIE 7823, Photomask Technology 2010, 782316 (24 September 2010); doi: 10.1117/12.868477

In this paper, we present an AFM based subsurface measurement technique that can be used for overlay and critical dimensions (CD) measurements through optically opaque layers. The proposed method uses the surface elasticity map to resolve the presence and geometry of subsurface structures. To improve the imaging performance of the AFM based subsurface measurements, we made use of photothermal excitation of the AFM cantilever together with a frequency modulation scheme. The experimental results show a significant improvement in the quality of the image, which leads to a more accurate and reliable CD and overlay measurement.

Extracting quantitative information about dimensions and material properties of buried structures is continuing to be an important but difficult task in metrology. Examples of questions asking for this capability include critical dimension metrology of fins such as the profile (bottom width, top width, height) or the presence and extent of voids. In recent years TNO has demonstrated the concept of using Atomic Force Microscopy (AFM) in combination with ultrasound to image buried structures based on their (visco-)elasticity in a technique called Subsurface Scanning Ultrasound Resonance Force Microscopy (SSURFM). We have successfully imaged structures less than 10nm wide, as well as structures buried up to a micrometer deep. However, extracting quantitative information from this data is not trivial, as the induced stress field in the sample depends on many parameters in a non-linear way: experimental parameters such as applied force, tip size and tip shape, and geometry and material properties of the buried structures themselves. Therefore, measurements based on this technique have a point spread function which varies in a complicated way with the sample properties that need to be measured. However, a solid understanding of the physics and mechanics involved, and the modeling of the expected structures and their response to externally applied stress, enable quantitative measurements. We specifically show our progress on characterizing a sample comprising fins from a 7nm node manufacturing test run.

The epitaxial growth of source/drain structures demands a process with tight control of boron and germanium composition to ensure consistent device performance. However, in-line monitoring of the epitaxial composition in FINFET structures has been one of the most difficult challenges for both process development and manufacturing. Traditional in-line monitoring schemes have relied heavily on critical dimension (CD) measurements, with no composition information. Instead, composition information was provided by offline analysis techniques such as secondary ion mass spectrometry (SIMS), which is destructive and does not measure the composition directly on the FinFET device structure. In this paper, we present results from in-line X-Ray Photoelectron Spectroscopy (XPS) measurements on FinFET structures. This technique is not only sensitive to individual element abundance but also gives information related to the local chemical environment. For this application we monitored silicon, germanium, and boron concentrations in SiGeB EPI source/drain 3D structure without interference from other structural features in the logic device. The in-line XPS measurement of PFET EPI boron and germanium performed in this way on the full structure transistor has been demonstrated to correlate with CMOS device performance, thus significantly reducing time to detect epitaxial composition drift or excursion.

Here we describe a methodology for molecular analysis at the nano-scale and present its capabilities. The analysis method is based on secondary ion mass spectrometry, SIMS, with gold nanoparticles (e.g. Au₄₀₀⁴⁺). The methodology presented here has unique features which enable molecular analysis at the nanoscale, namely the method of acquiring the mass spectrum and the nature of the impacting projectile. In the method a sequence of individual gold nanoparticles (Au₄₀₀⁴⁺) are used to bombard the sample, each impact results in ion emission from an area 10-20 nm in diameter. For each of impact of Au₄₀₀⁴⁺, the emitted ions are mass analyzed by time of flight mass spectrometry, detected and stored together in one mass spectrum prior to the arrival of the subsequent projectile. Each mass spectrum contains elementals, and molecules which were co-localized within 10-20 nm of one another. Examining the co-emitted ions allows to test the molecular homogeneity, and chemical composition at the nanoscale. We applied this method to a chemically amplified resist before and after exposure and development. After development the method was used to chemically characterize defect sites, which were not removed by the developing solution.

Background: The measurement of line-edge and linewidth roughness of small features for semiconductor manufacturing is commonly accomplished using a scanning electron microscope (SEM). But these measurements are biased by the noise inherent in SEM imaging.

Aim: Unbiasing of roughness measurements is best accomplished by taking advantage of the frequency characteristics of the noise to measure and subtract it out. This requires the ability to detect edges in a noisy SEM image without the use of standard image filtering techniques

. Approach: A physics-based inverse linescan model is used to robustly detect edges in high-noise SEM images without the use of filtering or image averaging. To validate the efficacy of SEM noise measurement and subtraction, rough features were measured under a wide variety of SEM settings, including number of frames of averaging and voltage.

Results: In all cases, the vast majority of the measurement bias was properly subtracted out. Over a wide range of SEM settings the biased roughness varied by more than a factor of two, but the unbiased linewidth roughness varied by only a few percent.

Conclusions: The approach of inverse-linescan edge detection followed by noise measurement and subtraction leads to reliable estimates of the true (unbiased) line-edge and linewidth roughness of features on the wafer. These unbiased estimates are quite insensitive to metrology tool settings over a reasonable range of values.

In the next generation SAOP (Self-aligned Octuplet patterning) process, the line width and LWR (Line Width Roughness) measurement of lines with sub-10 nm is required. We have already proposed a novel method of line width and LWR measurement with sub-nanometer uncertainty by using FIB (Focused Ion Beam) processing, and TEM (Transmission Electron Microscope) images as reference metrology. In the previous report, we applied the method to SAQP features. A specimen of the SAQP FinFET line and space device is coated with carbon and cut horizontally into a thin planar sample by the FIB sampling system. The thin sample is observed by using planar-TEM. The average PSD of LWR of SAQP FinFET sample at the upper and lower positions calculated from planar-TEM images. In this article, we apply the methodology to line width and roughness measurement of advanced features by SAOP process. The features are vertically or horizontally sliced as a thin specimen by FIB micro sampling system. LWR is calculated from the edges positions, and PSD (Power Spectrum Density) is analyzed for the reference metrology.

As the lithographically manufactured nanostructures are shrinking in size, conventional techniques, such as Scanning Electron Microscopes and Atomic Force Microscopes reach their resolution limits [1]. Novel inline scatterometry techniques not only provide the opportunity to bridge this gap, but they can also advance characterization of the lithographic process. The particular, Critical-Dimension Grazing incidence Small Angle X-ray Scattering (CDGISAXS) has emerged as one such promising modality to extract the profile of line gratings [2]. With the advent of brighter x-ray sources with tunable energies and faster detectors, there is a possibility for combining fast X-ray acquisition with high-speed data treatment to reach the timescale for an effective in-line characterization method. Due to recent progress in the ability to model data acquired from CD-GISAXS, we extended our model in order to study the impact of roughness. A set of twelve samples were studied. First, periodic line edge roughness (LER) and line width roughness (LWR) were measured, leading to the apparition of several semi-circle of Bragg spots as illustarted on Figure 1a. Using HIpGISAXS software, the GISAXS patterns were reproduced, allowing the extract of the periodicity of the roughness. On the second part of the line gratings, aperiodic roughness were designed with different frequencies and amplitudes. These samples led to the superposition of a semi-circle of Bragg spots with a “palm tree” feature coming from the profile of the gratings, illustarted on figure 1b. In a fist step, we extracted the in-depth profile of the gratings by fitting the modulations of the palm tree, in a similar approach as the CD-GISAXS one. In a second step, we modeled the impact of the roughness on the CD-GISAXS pattern and proposed a model to extract the roughness amplitude and frequency. References: [1] ITRS (2013). International Technology Roadmap for Semiconductors, http://www.itrs.net/. [2] Freychet, G. et al. (2018) Proc. SPIE, 10585, 1058512. [3] Freychet et al. (2018) Nanoscale Horizons, submitted. [4] Chourou, S. T., Sarje, A., Li, X. S., Chan, E. R. & Hexemer, A. (2013). J. Appl. Cryst. 46, 1781–1795.

We have previously demonstrated our method to obtain unbias dense line’s LER (Line Edge Roughness) processed by EUV (Extreme Ultra-Violet) lithography. No special edge-detection, simulation modeling, beam-scan, nor image processing is required, except optimization of beam-dose parameters. For instance, threshold method that is a conventional edge-detection is used on SEM (Scanning Electron Microscopy) image taken by a conventional beam-scanning with a conventionally used beam-conditions. However, especially for EUV-lithographed features we must determine carefully landing voltage and beam-dose that cause artificial reduction of LER and LWR (Line Width Roughness) due to shrink of photo resist materials. Note that we made edge-detection interval at every 5 nm, that is as small as probe-beam diameter. For instance, we set the vertical magnification, the pixel-density, and the sum-line-per-point parameter at 52.7k, 1024, and 2, respectively. Although we can make the interval as small as sub-nanometer, it is not reliable to measure the sub-nanometer object that is only one-tenth of the probe-beam diameter. Then, we verified accuracy of our unbiased LWR by using two independent experimental methods: TEM and FIB-SEM. We obtained spectra of PSD (Power Spectrum Density) from the TEM, the FIB-SEM and our unbiassing CDSEM-method. We found the three PSDs agreed very well to each others. This result strongly implies that three independent methods measured an identical PSD, of true LWR. By our unbiassing CDSEM-method we can measure the true LWR which is calculated from the true PSD. In this work, by using the similar experimental-methods we verify accuracy of our wiggling measurement. Wiggling is a hot issue in production yield of post dry-etch process. Especially about 20 nm or less in the line-width, wiggling starts appearing due to decreased elastic-stiffness of the line feature. A reason why we study the accuracy of LER, LWR, and wiggling is inline monitor of stochastic failures. As they increase significantly in EUV lithography process, production yield may not be promising. Bisshop et al. [1] investigated pitch and/or space-width correlate to incidence of stochastic-failures, such as breaking-line and bridging-line, down to ppm (parts per million). However, the incidence of the stochastic failures should be reduced less to ppb (parts per billion) or ppt (parts per trillion) which is as small as tolerable particle contamination on a wafer. This implies significance of accurate LWR and/or wiggling monitor because in narrow line or space a-few-nanometer-LWR narrows locally them the more and causes the more stochastic failures. In this work, in order to control ppb-stochastic failures we figure out a correlation between LWR and the failures’ incidence. We need to measure billions of features, that requires too long measurement time for practical process-monitor. To shorten the measurement time we test an effective method to estimate such very few number of failures. Reference [1] Stochastic effects in EUV lithography: random, local CD variability, and printing failures, Peter De Bisschop, J. of Micro/Nanolithography, MEMS, and MOEMS, 16(4), 041013 (2017).

In order to meet the tight Line Width Roughness (LWR) requirements for advanced metrology nodes, it is critical to be able to identify what the fundamental sources of roughness are, so that they can be individually minimized. In fact, more and more efforts aiming to decouple mask and / or metrology contribution from wafer data have been recently reported [1]. However, these approaches often rely heavily on extensive mask characterization, something that is not always easily available.

We propose here an alternative path to investigate and discriminate the root causes of LWR using only wafer data. It is based on Local Critical Dimension Uniformity (LCDU) decomposition [2], a methodology used to identify and quantify the individual LCDU contributors. The decomposition approach requires a smart sampling of the wafer print, in which an array of contact hole is measured in different dies multiple times. For such an approach to be successful, it is critical to ensure that the measurement locations are individually identified. Hence, it is necessary to anchor the metrology to a reference feature. A linear nested model [3] is then used to quantify the three main variability components (mask, shot noise, and metrology). This approach allows to sample thousands of features at mask, a task that would not be practically achievable through direct mask measurements.

In this work, LWR decomposition is implemented for the first time. To this aim, 18nm lines at 36nm pitch, printed by EUV lithography, were used. We specifically worked with a pattern including programmed defects, used as anchoring features for the metrology. In order to limit the impact of the metrology noise, expected to be higher for lines as compared to CH, we sampled over 8000 anchored measurements per image (in the CH case, only 81 measurements per image were needed). The LWR decomposition results indicated the dominance of the metrology noise, as expected. In addition, the mask contribution was observed to be less relevant that the shot noise.

To verify the accuracy of the LWR decomposition results, Power Spectral Density (PSD) analysis on wafer and mask SEM images was used. The metrology noise contribution was removed at both mask and wafer level using an un-biasing normalization of the PSD curves [4]. The comparison with the PSD analysis confirmed the feasibility of LWR decomposition, opening the way to a more effective diagnostic technique for roughness and stochastics.

For the most advanced nodes, line roughness reaches the same order of magnitude as the CD. It results in a huge impact on power consumptions and leads to some device failures. Hence, the control of this morphological aspect needs an adapted metrology. CD-SEM is considered as an adapted technique for roughness extraction. It is based on the PSD extraction that allows to obtain roughness information in frequency domain. CD-SAXS has been mentioned as one of the highest potential techniques for microelectronics by ITRS with an expected resolution better than one angstrom. The study presented in this article is based on programmed roughness simulations and first experimental measurements. It demonstrates that a complete PSD can also be extracted from a CD-SAXS analysis and that extended information of roughness can be so deduced. Comparison of SEM and SAXS proves the capability of SAXS technique for the PSD extraction of line roughness. Next challenges to improve this extraction are mentioned.

We have investigated the contributions of surface effects to Monte Carlo simulations of top-down scanning electron microscopy (SEM) images. The elastic and inelastic scattering mechanisms in typical simulations assume that the electron is deep in the bulk of the material. In this work, we correct the inelastic model for surface effects. We use a model for infinite flat surfaces, and apply it to non-flat, but smooth, geometries. Though this is a simplification, it captures most qualitative differences to the bulk model, including coupling to surface plasmons. We find that this correction leads to an increased SE signal near a feature’s sidewall in low-voltage critical dimension SEM (CD-SEM). The effect is strongest for low beam energies. Due to some of the assumptions in our model, we are unable to quantitatively predict the extent by which the signal from the sidewall is enhanced. The enhancement of signal from the sidewall may be large enough to cause the measured edge position to shift significantly.

My apologies, the technical abstract will be submitted next week.

With the rapid advancement of the CMOS technology in the semiconductor industry, innovative device fabrication techniques have led to the development of Nanosheet (NS) FETs and Nanowire (NW) FETs with sub nm dimensions. The application of Mueller Matrix Spectroscopic Ellipsometry (MMSE) based scatterometry simulations to characterize these complex 3D structures is described. Optical model-based simulations were used to investigate sensitivity and limitations of MMSE to characterize small changes in the etching of these NWTS structures. Cross-sectional Scanning Electron Microscopy and Tunneling Electron Microscopy provided a reference technique for the scatterometry simulations. Additionally, sensitivity to the nanowire test structure shape, size of holes, nanosheet thicknesses of each layer and the rounding at the top of the structure were investigated. As a result of this study, we find that Mueller Matrix scatterometry has the sensitivity to monitor dimensional changes during the progression of the selective SiGe etch for the sub surface nanowires and thus provide a reliable measurement method for process control.

In the microelectronics industry, most of the dimensional metrology relies on Critical Dimension (CD) estimation. These measurements are mainly performed by Critical Dimension Scanning Electron Microscopy (CD-SEM), because it is a very fast, mainly non-destructive method, and enables direct measurements on wafers. To measure CDs, the distance is estimated between the edges of the observed pattern on a SEM image. As the critical dimension becomes smaller and smaller, the needs for more reliable metrology techniques emerge.

In order to obtain more meaningful and reproducible CD measurements regardless of the pattern type (line, space, contact, hole . . . ), one needs to perform a CD measurement at a known and constant height thanks to a methodology that determines the topographic shape of the pattern from SEM images. A SEM capable of bending the electron beam (up to 12° in our case) allows to catch images at different angles, giving access to more information. From the analysis of such images, pattern height and sidewall angles can be consequently determined using geometric considerations.¹

Understanding interactions between 3D shapes, pattern's material and the electron beam, becomes essential to correlate topography information. A preliminary work based on Monte-Carlo simulations was conducted using JMONSEL, a software developed by the NIST.

Thanks to this analysis, it is possible to determine theoretical trends for different topographies and beam tilt conditions. Thanks to the effects highlighted by simulations, the processing of the tilted beam SEM images will be presented, as well as the method used to create a mathematical model allowing topographic reconstruction from these images. Finally some reconstruction using this model will be shown and compare to reference measurements.

The overall flow used to process images is presented. First, images are transformed into grayscale profiles in order to process them. After a smoothing procedure, positional descriptors are computed for specific profile derivatives values. Then, from these descriptors coming from two images of the same pattern taken at different tilt angles, we use a low-complexity linear model in order to obtain the geometrical parameters of the structure. This model is created and calibrated thanks to JMONSEL simulations and then re-calibrated on real silicon patterns.

We demonstrate that the use of real SEM images coming from real silicon patterns with our model leads to results that are coherent with conventional 3D measurements techniques taken as reference. Moreover, we are able to make reliable reconstructions on patterns of various heights with a single calibrated model. Our batch of experiment shows a 3-sigma standard deviation of 13% on the estimated height.

We also show, thanks to simulations, that we are able to reconstruct the corners rounding (CR) from SEM images. However, because our wafer do not present a variability, the CR measurements still need to be assessed.

Undetected patterning defects on semiconductor wafers can have severe consequences, both financially and technologically. Industry is challenged to find reliable and easy-to-implement methods for defect detection. In this paper we present robust machine learning techniques that can be applied to classify defect images. We demonstrate the basic principles of an algorithm that uses a convolutional neural network and discuss how such networks can be improved not only in their architecture but also tailored to the specific challenges of defect inspection through more specialized performance metrics. These advances may lead to more cost-efficient measurements by adjusting the decision threshold to minimize the number of wrong defect detections.

Defects are ubiquitous in the semiconductor industry and detection, classification at various levels is a challenge and requires rigorous sampling. Every technology offers a new challenge in this area and requires numerous hours of setup, debug time for semiconductor integrated chip manufacturers. Intentional defects on patterns at various sizes in comparison to the critical dimension of a particular technology are used to preview their modulation and assess inspection tool performances. Figure 1 shows a few types of intentional defects as designed and their respective manifestation on a photomask. The chart also shows detection and printability limit and it varies by each defect type.^{1, 2}

In recent years deep learning has made tremendous progress and has substantially improved the state-of-art in many applications that include object detection, speech recognition, and image classification³ The application and design of these deep learning tools in semiconductor defect recognition can be very useful, as it has the potential to reduce the setup time, cost and improving the overall (defect) detection and classification accuracy.

In this work we demonstrate the application of convolution neural networks on e-beam images of intentional defects on various types of patterns. We assess various filters and their outputs at each layer of a custom convolutional neural network (Figure 2) to ultimately improve the architecture and its accuracy. We also demonstrate the relative effectiveness of transfer learning in this application with limited availability of labelled data. Using the architecture illustrated in Figure 2 we are able to achieve a classification accuracy of 95%.

Optical scatterometry is a method to measure the size and shape of periodic micro- or nanostructures on surfaces. For this purpose the geometry parameters of the structures are obtained by reproducing experimental measurement results through numerical simulations. We compare the performance of Bayesian optimization to different local minimization algorithms for this numerical optimization problem. Bayesian optimization uses Gaussian-process regression to find promising parameter values. We examine how pre-computed simulation results can be used to train the Gaussian process and to accelerate the optimization.

With the miniaturization of devices, hot spots caused by wafer topology are becoming a problem in addition to hot spots resulting from design, mask and wafer process, and hot spot evaluation of a wide area in a chip is becoming required. Although DBM (Design Based Metrology) is an effective method for evaluating systematic defects of EUV lithography and multi-patterning, it requires a long time to evaluate because it is necessary to acquire a high-SN SEM image captured by a contour extraction for DBM that can handle low-SN SEM image captured by high-speed SEM scanning conditions.

Contour extraction using deep learning possesses high noise immunity and excellent pattern recognition ability, and demonstrates high performance to contour extraction from low SN SEM images and multiple layers pattern ones. The proposed method is composed of annotation operation of SEM image samples, training process using annotation data and SEM image samples, and contour extraction process using the trained outcome. In the evaluation experiment, we confirmed that satisfactory contours are extracted from low SN SEM images and multiple layers pattern ones.

As the design node of memory device shrinks, OPC model accuracy is becoming ever more critical from development to manufacturing. To improve the model accuracy, more and more physical effects are analyzed and terms for those physical effects are added. But it is unachievable to capture the complete physical effects. In this study, deep neural network is employed and studied to improve model accuracy. Regularization is achieved using physical guidance model. To address overfitting issue, high volume of contour based edge placement (EP) gauges (>10K) are generated using fast eBeam tool (eP5) and metrology processing software (MXP) without increasing turnaround time. It is shown that the new approach improved model accuracy by >47% compared to traditional approach on >1.4K verification gauges.

As industry prepares to introduce extreme ultraviolet (EUV) technology for the coming sub-10-nm lithography, this paper presents metrology approaches that utilize the prevalent Critical Dimension Scanning Electron Microscope (CD-SEM). Two technical approaches will be discussed. One is comprehensive solutions for new EUV characterized features, such as low resist-shrinkage electron beam optics and high efficiency metrology/inspection for EUV process monitoring. The other, like conventional minimization processes, is down-to-ångström-order metrology methodologies required for stricter CD process control. This paper is the first to conceptualize specifications for a stringent and multi-index tool matching, namely “atomic matching,” which is considered as a crucially important feature of any in-line metrology tools in the EUV era.

In-line metrology for measuring 3D features of the high aspect ratio (HAR) holes is becoming more challenging due to the development of semiconductor technology, particularly in memory devices. Measurements of the bottom critical dimension (CD), taper angles, and 3D profiles of the HAR holes require new imaging capabilities.

In this work, we explore backscattered electron (BSE) imaging and its applicability in 3D metrology of the HAR holes. Monte Carlo simulations were performed to estimate the BSE signals emitted from the HAR holes. The simulation results demonstrate that the BSE signal intensity decreases exponentially with increasing the depth of the irradiated location in the HAR holes. Based on the characteristics of the BSE signal intensity, an algorithm utilizing depth-correlated BSE signal intensity was proposed for the 3D metrology of the HAR holes. Furthermore, several types of holes with different taper angles and different bowing profiles were fabricated and experiments were performed to verify the feasibility of the proposed algorithm. The cross-sectional profiles of the fabricated holes which are created using the BSE profiles are matching with the as-cleaved cross section observed by X-SEM. These results demonstrate that the 3D-profile variation of the HAR holes induced by the etching processes can be identified by our approach.

Deep-learning-based SEM image denoiser Dorin Cerbu1, Sandip Halder1, Philippe Leray1 1IMEC, Kapeldreef 75, B-3001 Leuven, Belgium We report the development of a new method to denoise SEM images with the help of artificial neural networks. Upon using a preprocessing and training scheme tailored for SEM images of structures, most often encountered in semiconductor manufacturing, we can efficiently denoise images affected with varying degrees of noise severity and origin. In the figure below, we show an example of how we can use this filter efficiently to treat noisy images and improve the image quality. This can help in acquisition of more stable and better metrology data. Fig1(a) original image (b) Image which has been denoised using deep-learning based algorithms This development is of utmost importance for the case of post-litho processing step where resist nanostructures when SEM inspected are usually impacted by the electron beam and shrink, hence skewing critical dimension measurements. This is especially true as we push towards sub N-10 nm nodes. Application of our deep-learning processing scheme allows efficient noise reduction on SEM inspection images and helps us discern minor details previously shadowed by noise. This is extremely important as we move towards using EUV in high volume manufacturing. Small details can be crucial to understand the root-cause of stochastic and process defects. In previous work, we have already shown different approaches to understand stochastic defects [1-2]. The goal of this work is to enhance the image quality as much as possible to gain further fundamental understanding on nano-defects. [1] S. Halder et. al., ‘Using machine learning techniques to understand EUV stochastics, SPIE Photomask Technology + Extreme Ultraviolet Lithography, 2018 [2] K. Sah et.al., ‘EUV stochastic defect monitoring with advanced Broadband optical wafer inspection and e-Beam review systems’, SPIE Photomask Technology + Extreme Ultraviolet Lithography, 2018

Nowadays, the accuracy of the metrology is becoming more and more a critical issue for microelectronic manufacturing as new technology nodes necessitate more and more rigorous process control. Scanning Electron Microscope (SEM) is the equipment most typically used to measure pattern dimensions. The aim of this study is to model and simulate a synthetic SEM image. This is fulfilled by taking into account the physical phenomena that take place in the sample during the scanning of the electron beam. The considered phenomena are the kinetics of the drift and the diffusion of the charges during the scanning and the secondary electrons emission from the sample into the vacuum. A system of Partial Differential Equations (PDEs) is obtained which defines a system that will be solved using the Finite Element Method. The escaping of the secondary electrons is modeled by applying a Robin boundary condition on the top surface of the sample. By computing the secondary electron emission that originates from the sample during the beam scan, a synthetic SEM image is created.

Device miniaturization and complication is now stimulating the strong needs for the three dimensional (3D) geometry measurement of the structure. Now in the single-nanometer nodes, the CDs need to be known at multiple pattern heights especially in after-etch inspection. This means SEM measurements is expected to provide 3D contours. Unfortunately, CD-SEM is basically top-down imaging tool, therefore the acquired micrograph is the 2D projection of the device structure. Meanwhile, optical CD (OCD) works well to deduce the 3D geometrical parameters. Due to the spot size limitation, however, it is hard to obtain the local variation of the structure, or hard to access in-die metrology data. While TEM or slice and view by FIB-SEM is a reliable option to see the local 3D structure, they are destructive and low in statistics due to the long turn-around time. Therefore the challenge is, how to obtain in-die 3D geometrical information in non-destructive way. The purpose of the present work is to extend CD-SEM capability to extract 3D geometry. The most intuitive approach is the direct imaging, where the structure can be extracted directly from the acquired image. The direct imaging includes, beam tilt SEM and topography detector. While the beam tilt is an intuitive method, at larger tilt over 10 degrees the image blur is unavoidable and the precise metrology application is difficult unless the small tilt angle is enough to see the side wall structure like high-aspect-ratio (HAR) structure over several microns in depth. Topography detector is another well-known approach, and works well for the isolated target like particles or pattern defects. In the smallest spacing, however, characteristic shadow is not created, and the topography extraction is basically difficult. By these reasons, we especially have a strong interest in indirect methods described below. Indirect approach includes model-based geometry matching and hybrid metrology with other reference measurements. In these approaches, it is required to find the characteristic SEM waveform or signal intensity (gray-level) which are sensitive to the target geometry. The sensitivity of the response can be estimated by the simulation models, or the comparison with other 3D measurements tools like OCD or AFM. The concept is the generalization of the model-based library (MBL), where the SEM waveform is compared with pre-calculated library of the waveforms. In our approach, calibration could be done by using simulation data or real 3D profiling data. Another generalization is that a SEM operation condition is also altered to enhance the sensitivity of all the geometrical parameter. For example, by sweeping the beam voltage, the multiple waveforms are obtained and the low voltage data has a sensitivity in the pattern top geometry, and the higher voltage data in the pattern bottom. Similar parameter sweep can be applied to energy-filter voltages or focus heights. It is expected that this sort of the generalization enhances the correctness of the geometry profiles. In the conference presentation, we will compare these 3D measurement approaches and discuss how to realize the reliable in-die 3D measurement in the coming advanced technology nodes.

Over the past few years, patterning edge placement error (EPE), which combines information on variability of pattern sizes and placement between adjacent device layers, has been established as the key metric for patterning budget generation and holistic patterning control. More recently, the emergence of high-throughput SEM tools that provide inspection and large-volume CD metrology capabilities has enabled unprecedented statistical analysis of on-product pattern variability.

In the current paper we address edge placement budget generation as well as potential for improved patterning control for an HVM use case at the 28nm litho node. Edge placement and possible related defect mechanisms arise most critically at the contact layer, where contact hole patterning and EPE, with respect to both underlying gate and active layers need to be well controlled. At the 28nm node and for automotive applications, variability control within 5-sigma, i.e. to failure rates below 1 ppm, is generally required to ensure device reliability.

To support generation of an EPE budget by wafer data that captures inter and intra-field components, including local stochastic variations, we use a high-throughput, large field-of-view SEM tool from Hermes Microvision, at all three process layers of interest, as well as YieldStar metrology for overlay characterization. The large volume of data being made available -tens of millions of individual CD measurements- allows mapping out the low-probability ends of variability distributions and detecting non-Gaussian ‘fat tails’ indicative of defect rates that would be underestimated by 3-sigma estimates. Data analysis includes decomposing the total pattern variations into sources of variability, such as global CDU, mask variations and local stochastics. In addition to established CD metrology, we apply novel SEM image based analysis of repetitive patterns in SRAM arrays to generate 2-dimensional process variability bands, including estimates of pattern placement. This approach allows to investigate in detail the probabilistic interaction between active, gate and contact layers.

A depth measurement technique for extremely deep holes (such as channel holes in 3D flash memory devices)—by using back-scattered-electron (BSE) images obtained by a high voltage critical dimension scanning electron microscope (CDSEM)— was developed. A high voltage CD-SEM can detect BSEs that penetrate solids surrounding deep holes. These BSE images include rich information concerning the bottom structures of deep holes. As the BSEs lose their energies according to the distance they travel in solids, it is deduced that the BSE image intensity at hole bottoms depends on hole depth. In a feasibility study on depth measurement using an SEM simulator, it was found that the intensity also depends on hole diameter. The relationship between BSE intensity, hole depth, and hole diameter was modeled by simplifying a backscattering model and approximating the target medium by volume density. Based on this model, a depth measurement technique using only a top-view BSE image is proposed. Measurement error of the technique for channel holes of a 3D flash memory device with depths of a few microns was evaluated by using a high voltage CD-SEM. According to the results of the evaluation, error range was 62 nm and measurement repeatability was ± 18 nm. It is concluded that these values are sufficient for detecting depth defects. This technique achieves fast and non-destructive depth measurement of individual extremely deep holes.

The scaling of device dimensions has resulted in a need for high resolution metrology techniques capable of measuring small CDs with a high degree of precision and accuracy. Scanning transmission electron microscopy (STEM) has previously been demonstrated to be a metrology technique capable of measuring small CDs and gathering large volumes of accurate and precise metrology data. In addition, energy dispersive X-ray spectroscopy (EDS) metrology has also been demonstrated to be a powerful technique enabling the detection and measurement of low contrast layers, specifically for 3D NAND devices. Benchmarking EDS metrology against STEM metrology in terms of precision and accuracy is important to further investigate the capabilities of EDS metrology for the semiconductor industry. This study was performed using the latest technology in EDS detectors, along with automated acquisition and metrology software to generate large metrology data sets on horizontal nanowire structures. In this paper, we present data to support our finding that EDS metrology is well-matched with STEM metrology in terms of both precision and accuracy. In addition, we discuss the capability of EDS and STEM metrology to detect subtle process variations in next-generation logic devices.

A CD-SEM metrology for an EUV resist that was compatible with low shrinkage and high spatial resolution was investigated by using primary electrons (PEs) with high energy. The shrinkage and an image sharpness were evaluated for the EUV resist using PEs with energies of 200, 800, and 4000 eV. As a result, the smallest shrinkage and image sharpness were obtained under the condition of PEs with an energy of 4000 eV. We believe that a high-voltage CD-SEM is a potential candidate for CD metrology tools in the EUV lithography era.

Overlay process control is a critical aspect of integrated circuit manufacturing. Advanced DRAM manufacturing overlay error budget approaches the sub-2nm threshold, including all sources of overlay error: litho processing, non-litho processing, metrology error, etc. Overlay measurement quality, both for accuracy and robustness, depends on the metrology system and its recipe setup. The optimal configuration depends on the layer and materials involved. Increased flexibility of metrology setup is of paramount importance, paired with improved methods of recipe optimization.

Both optical image-based overlay (IBO) and scatterometry diffraction overlay (SCOL®) are necessary tools for overlay control. For some devices and layers IBO provides the best accuracy and robustness, while on others SCOL provides optimum metrology. Historically, wavelength selection was limited to discrete wavelengths and at only a single wavelength. At advanced nodes IBO and SCOL require wavelength tunability and multiple wavelengths to optimize accuracy and robustness, as well as options for polarization and numerical aperture (NA). In previous studies^1,2,3 we investigated wavelength tunability analysis with landscape analysis, using analytic techniques to determine the optimal setup. In this report we show advancements in the landscape analysis technique for IBO through both focus and wavelength, and comparisons to SCOL. A key advantage of imaging is the ability to optimize wavelength on a per-layer basis. This can be a benefit for EUV layers in combination with those of 193i, for example, as well as other applications such as thick 3D NAND layers. The goal is to make accurate and robust overlay metrology that is immune from process stack variations, and to provide metrics that indicate the quality of metrology performance. Through both simulation and on-wafer advanced DRAM measurements, we show quantitative benefits of accuracy and robustness to process stack variability for IBO and SCOL applications.

Methodologies described in this work can be achieved using Archer™ overlay metrology systems, ATL™ overlay metrology systems, and 5D Analyzer® advanced data analysis and patterning control solution.

The aim of this work is to clarify the quantitative relationship between the Edge Placement Error (EPE) and Line Edge Roughness (LER) in a rough pattern. Using a computational modelling approach to isolate this relationship, we show that despite the dominant role of Rms(LER), EPE is also affected by the correlation length especially at long length of interests. Similarly, we demonstrate and quantify the positive correlation of the edge correlation coefficient with Image Placement Error. The ultimate concern is to get design-rule determinations based on EPE definitions and characterization which is informed by modern manufacturing and metrology aspects of LER.

The on-product overlay roadmap demands an aggressive overlay requirement in the advanced node. Currently the on-product overlay is dominated by effects coming from wafer processing and overlay target detectability. Processing effects such as symmetric stack variation and asymmetric overlay target deformations are expected to become limiting for accurate overlay measurements in future nodes

. Increased accuracy requirements and overall complexity in product stacks require a sensor with a higher flexibility. To address this an advanced metrology system is introduced in the fab, providing full flexibility in the selection of measurement wavelengths. On top of the wavelength flexibility, the increased wavelength switching speed enables the use of asymmetry robust recipes by combining multiple wavelength measurements at each overlay target.

In this paper we will introduce a method to select the most accurate multi-wavelength recipe that provides significant improvement in accuracy compared to the best single wavelength recipe. We will introduce KPIs to monitor the health of the multi-wavelength measurement. The KPIs are reported per site indicating the accuracy for every measured point.

Additionally we will show our steps towards the recovery of the points flagged by multi-wavelength KPI by a combination of measuring more wavelengths and an accuracy guided region of interest selection.

Overlay is one of the most critical design parameters in integrated circuit manufacturing. Maintaining good overlay performance during manufacturing is therefore essential in order to obtain high yield and to ensure that the performance and reliability of the eventual semiconductor device is according to specifications. For that reason, optical metrology is nowadays extensively used in any production facility for overlay monitoring and process control. Overlay metrology is typically required after each lithography step for (nearly) every lot. The number of process and lithograpy steps have increased significantly with advancing technology nodes and consequently there is an increased demand for overlay metrology. Although the benefits of overlay metrology are obvious, the use of metrology should be kept at acceptable levels as it adds cost and increases fab cycle time. Virtual overlay metrology, the replacement of some real overlay measurements with predicted values, is an effective solution for keeping the need for overlay metrology under control.

One of the contributors to layer-to-layer overlay in today’s chip manufacturing process is wafer distortion due to thin film deposition. Mismatch in the film specific material parameters (e.g., thermal expansion coefficients) may result in process-induced warpage of the wafers at room temperature. When these warped wafers are loaded onto the scanner for the next layer exposure, in-plane distortion patterns may be apparent after clamping. The wafer alignment system inside the scanner is designed to correct for these process-induced in-plane wafer distortion signatures. Depending on the complexity of the distortion pattern, the choice of wafer alignment model can be adapted to achieve the required overlay performance. While wafer overlay metrology is used to correct for the systematic part of the wafer distortion, the wafer alignment functionality addresses the random part that is varying from wafer-to-wafer.

In the case of a homogeneous single film of uniform stress deposited on a substrate at elevated temperatures inside a deposition tool, the resulting free-form wafer shape at room temperature will take a parabolic form (either bowl or umbrella). The resulting in-plane distortion can be described by a radial scaling pattern. A linear wafer alignment model can easily correct for these kinds of distortion patterns and the resulting overlay is close to the scanner baseline performance. Also, in the case where there is a slight variation in one of the material parameters across the wafer, the resulting wafer distortion can easily be corrected for by selecting one of the available wafer alignment models. A Higher Order Wafer Alignment model up to the third order (HOWA3) has been proven to be sufficient to bring the overlay performance down to the scanner baseline performance over the past years.

In this paper we will consider the impact of local stress variations on the global wafer deformation. One of the sources of the local stress variation is linked to the intra-field or intra-die pattern density. We will demonstrate that the intra-field stress distribution not only affects the intra-field overlay performance but has also a significant impact on the global wafer distortion. The focus will be mainly on use-cases with high intra-field stress variations similar to what is encountered in 3D-NAND processes. These cases in particular need a more advanced correction approach. However, since the underlying root cause is generic, the same approach may also be applicable to other use-cases like DRAM and Logic.

In the past few years, Artificial Intelligence (AI) has been a subject of intense media hype. Machine learning, deep learning (DL), and AI come up in countless articles, often outside of technology-minded publications. As the AI hype keeps growing, it is important to be able to recognize the signal in the noise, to tell apart world-changing developments from what are merely over-hyped press releases. This paper tries to explain how deep learning is working and how GPU (Graphic Processing Unite) can make it a reality. Finally, in-memory computing (IMC) for DL is introduced to point out future high performance and low power DL hardware development direction.

Introduction and problem statement Given that EUV lithography allows printing smaller Critical Dimension (CD) features, it can result in non-normal distributed CD populations on ADI wafers [Civay SPIE AL 2014], leading to errors in predicted failure rates [Bristol SPIE AL 2017]. As a result, there is a need to quantify the actual behavior of the CD population extremes by means of massive metrology [Dillen EUVL 2018]. Not only allows this to study the CD distribution, we can in parallel also evaluate pattern quality and the failure mechanisms leading to defects. This massive metrology method provides an accurate failure rate based on CD, and enables new possibilities to define a failure rate based on different metrics in a single measurement. Method We analyze the CD uniformity of pillars in polar coordinates using a global waveform based thresholding strategy. In conjunction with this CD information, we also evaluated the print quality of each individual measured feature. Fig 1. In line detected anomalies and failure definitions As we gather this information during the measurement of CD, we can limit the additional measurement overhead to neglectable levels. Application and outlook We will show how we can leverage this to determine a defect based process window and relations of failure mechanisms through process conditions (see figure 2). When we take failures in a CH dataset into account, we illustrate the effect on the shape of a large dataset distribution in figure 3. Fig 2. Defect identification for a through exposure dose experiment of pillars. For each condition >13k pillars where measured. The plot clearly shows an asymmetric behavior due to different failure mechanisms at low and high energy. The 2 vertical lines at relative energies 0.93 and 1.05 times nominal indicate the low defect process window. Fig 3. A distribution of measured regular grid dense CH. The red line is the unfiltered CD data, the blue line is the shape of the distribution after filtering individual CH measurements that have a much lower contrast than expected.

Optical Proximity Correction (OPC) modeling has evolved throughout the years to address 2D edge placement corrections, driven mainly out of CDSEM measurement results. 3D pattern modeling, and 3D-OPC for resist pattern, is much more complex. 3D information can be obtained by Optical CD tools for large repetitive arrays, where the outcome is an averaged 3D profile, or by Atomic Force Microscopy (AFM), offering accurate local in-die 3D metrology but can be limited by tip size and can also involve long scan times. In recent years we have presented a 3DSEM imaging methodology using multiple detectors to reconstruct surface morphology. To address the 3D-OPC model characterization challenge we combine in this work two metrology methods; AFM as a reference tool, and 3DSEM. Both metrology techniques provide nondestructive, large statistical sample measurements, across the wafer for lithography process window characterization, and 3D-OPC model calibration. Parameterized test patterns were generated on mask by Synopsys and printed on wafers at IMEC. Selective patterns were measured by 3DSEM and AFM to optimize 3DSEM measurements. Statistically significant 3DSEM measurement results were used for 3D-OPC model calibration, offering 3D-OPC corrections including resist shrink induced by SEM imaging.

In semiconductor fabs, electron microscopes are key equipment for metrology, failure analysis, physical characterization and defect review classification. In a wafer fab like ST Crolles 300mm, CDSEMs are generating more than 20 Million of images per year. The image is by itself a raw material on which the metrology is performed. It is needed to get access to CD which is very often a single value extracted. If the CD is in specification, it is very unlikely that someone will look at the picture. If someone would do so in a systematic way, it would see that there is much more information available in the image than a single CD value. Unfortunately, most of this information passes under the radar of SPC charts and is somehow wasted.

This paper presents results obtained by CDSEM image contour analysis from various kind of technologies and applications in manufacturing in our fab. These results show that images contain significant amounts of information that can be extracted and analyzed using an efficient contour extraction and analysis toolbox.

Process variability of complex shapes can be shown, robust layer to layer metrics can be computed, pattern shifting, shape changes, image quality and many others too. This opens new possibilities for process control and process variability monitoring and mitigation.

With the Area Selective Deposition (ASD) technique, the material is deposited on desired areas of the sample surface. The control of such process implies accurate characterization of the deposited material on both growth and non-growth surfaces. This requires, first a good measurement capability to quantify the geometry of the deposited layer, and second, a proper assessment of the process selectivity. In this work, we show how to combine two complementary measurement techniques to overcome their individual inherent limitations¹ for ASD applications. Scatterometry, the first measurement technique, has been applied to the characterization of the deposited layer geometry properties because of its high sensitivity to dimensional features and material. To complement the ASD performance characterization with the local information, Atomic Force Microscopy (AFM) has been used to access the topography details of the analyzed surfaces. We have analyzed the AFM images with the power spectral density (PSD) approach to identify undesired material deposition in the non-growth area and thus to characterize process selectivity through the comparison to a reference sample. Experimental validation of the scatterometry and AFM techniques for ASD applications has been done on wafers having various selectivity levels. The scatterometry metrology measured accurately the thickness of the deposited layer on both growth and non-growth areas when the deposited layer became uniform. The lateral overgrowth was quantified as well with the same technique and showed some changes from process condition to another. In addition, the PSD analysis applied to the AFM images was able to probe minutely the nanoparticles nucleation on the non-growth area and as result has revealed the selectivity transition regimes. Later, we have built a hybrid model by the combination of the 2 metrologies results and validated its predictions on test wafers.

Power Spectral Density (PSD) is now a standard analysis for pattern roughness process control in advanced patterning. Due to PSD analysis sensitivity coupled with Scanning Electron Microscopy (SEM), line edge roughness (LER) and line width roughness (LWR) are more understood. However, this is applied on sides of the line, and has limited information about roughness on top of the pattern. On the other hand, Atomic force microscopy (AFM) measure accurately the topography of pattern and even if this metrology is probe size dependent, the top of the patterned lines is well revealed when trenches are too narrow to be measured. In this work, we have adapted and applied the PSD analysis on patterned lines measured by AFM. Specific algorithm has been developed to localize the analysis on top of the line. This allow us to report on the effect of processes, such EUV resist smoothening and Area Selective Deposition (ASD).

To reduce defocus from leveling errors at the wafer edge, modern exposure tools offer a broad range of advanced leveling controls. These can be explored fully with minimum experimental effort by simulating alternative set-point curves (z; R_x; R_y) and resulting MA and MSD focus residuals from existing full wafer height maps. In this paper, optimizations are carried out to obtain the best focus edge clearance settings for several DRAM and NAND products, across different layers and exposure tools. The simulated die-fine focus errors are compared to the POR settings and verified with electrical results. Differences across products, layers, and exposure tools are discussed.

Since the beginning of the Crolles 300mm fab, more and more complex logic technologies, down to 28nm node, have been developed. At the same time, the products mix increased at a very high level : Specifically for the lithography area, this complexity leads to an intricate management of thousands of masks, hundreds of track process recipes, used on various lithography clusters types (193nm including immersion, 248nm and 365nm). In order to apply the best process parameters, APC software is used since many years, and was continuously improved. It now takes into account multi-variate parameters coming from various process contexts. A new sampling tool was developed to adjust the measurements control plan. All kind of in-line measures are addressed (thickness, critical dimensions, overlay…). Since the beginning of this software development, the approach was to keep in mind the APC model. The objective was to use the APC data’s (alarms and warnings) to secure the sampling decisions without compromising the regulation loops stability.

This sampling tool can use different inputs (production, tools, APC…) in a dynamic way. This means that the system is dynamic for both process and metrology aspects, and can be adapted to integrate different variables and external events. A real time communication flow was created between APC and sampling tool. Even if the measurement skip decision is taken by the sampling tool, the APC feedback is systematically requested when run to run is involved, like for all lithography process steps. The strength is to deal with high products / mix complexity and react in real time to new product introduction, process deviation, atypical lots including R&D projects and sudden change of the products mix. Both tools are so linked that the sampler remains invisible. Process engineers continue to manage and control lithography process through APC tool mainly.

In parallel, different alarms and triggers have been implemented, including a specific “crisis” mode to quickly respond to the metrology equipment loading or availability variability.

The sampler introduction allowed an optimization of the metrology toolset costs and lot cycle time improvement. Also as a consequence, a more efficient metrology control plan, with an optimized balance between process criticality and metrology requirements.

Future opportunities are related to more dynamic behaviors, as a dynamic sampling rate adapted to metrology capacity, function of the real time metrology capacity or sampling decision dynamically based on process variability components.

EUV lithography has been adopted in most advanced semiconductor manufacture fabs, enabling the next step in design rule scaling. With this progress, minimum critical defect size has become smaller and harder to detect. Defect inspection equipment suppliers must therefore in parallel provide a significant step up in inspection sensitivity at a reasonable throughput. Optical inspection tools are facing an unprecedented challenge because defects less than 10nm are not optically visible. As an alternative, semiconductor manufacturers have turned toward e-beam inspection. E-beam inspection is widely used in R&D to shorten development cycle-time and selectively used in high volume manufacturing (HVM) for process monitoring, however currently it is not fast enough for large-scale replacement of optical inspection. Our approach to address this shortcoming is to combine cutting edge multiple-beam technology with a cutting edge positioning system/computation architecture to create a next generation e-beam inspection system capable of scanning with multiple electron beams at the same time. This paper reports on the progress in developing such a system as well as future multi-beam inspection applications.

Stochastic effects in EUV patterning refer to random variations that impact local pattern edge fidelity. It can be caused by the lithography or etch processes. Distorted edge placement can result in larger pattern edge roughness, distorted pattern shape for contract holes, poor CD uniformity, and in more severe cases, partially or fully closed contacts. Large statistical SEM metrology can be used to quantify the severity of distortion and failure probability by measuring line edge roughness (LER) and line width roughness (LWR) [3].

The attempt to differentiate between normal global uniformity and local uniformity pose a metrology challenge. In this paper, we present a scanning electron microscopy (SEM) based method for detecting stochastic defects. The detected defects are reviewed by metrology and classified by defect margin merit. The proposed merit converts geometrical attributes into statistical attributes which identify whether a pattern is statistically normal or a statistical outlier.

Voltage contrast (VC) is a long known and well established technique to give combined inline sensitivity to electrically relevant measures of defectivity but also local defect isolation and integrated review SEM making the technique a critical piece of fab wafer inspection. By creation of a special mark design with many local repeats of different CD and overlay set points a voltage contrast response is created which allows the local edge placement error population to be estimated while also capturing a connectivity and isolation yield proxy. This enables high throughput local estimates of overlay, CD, overlay and CD process window and local CD uniformity. A test mask containing these marks was designed and fabricated at IMEC with metrology done on optical and electron beam inspection systems. Both open and short sensitivity are programmed into the marks and this yield proxy data has inherent value on its own. We propose to integrate these special test marks into some critical layers in modern memory and logic process flows with a design which can be added to scribe lines or empty regions/in die test structures in logic or empty regions of the memory periphery. Significant design and process knowledge is required to design a mark which can integrate with the process and give good EPE sensitivity. Initial mark designs have been targeted at single damascene copper on tungsten with VC inspection after copper polish. Initial results show a high baseline yield loss but also show clear and intuitive CD and Overlay process window quantification from the VC EPE marks. Marks as large as ~100,000 um2 and as small at 250um2 have been designed and enable overlay, CD, LCDU and with yield sensitivity to ~1 part per million for the larger marks and ~1% for the smallest marks. With the expected productivity of the ebeam inspection system we should be able thousands of marks per wafer or field to support diverse overlay, CD and control use models and process fingerprint mapping.

With the adoption of extreme ultraviolet (EUV) lithography in high volume manufacturing (HVM) to enable the sub-7nm scaling roadmap, defect characterization brings new challenges and learnings. Traditional approaches to process window discovery (PWD) methodology developed^2,3,4 using broadband plasma optical inspection also hold in the realm of EUV lithography. Although there is substantial depth of focus for regular patterns, focus continues to be an important modulation parameter for logic patterns. Dose is an important modulation parameter especially due to stochastic defects.¹ Further, overlay is another important parameter when it comes to hybrid integration schemes such as self-aligned quadruple patterning (SAQP) and EUV block patterning, for example, in BEOL layers. In this paper, we will discuss PWD results on a foundry N5 equivalent M2 layer, studying both SAQP and block integration with direct EUV patterning. We also demonstrate the impact of EUV stochastics to the overall process window and develop useful analysis methodologies.

The authors report on critical dimension metrology on nanoscale gratings by means of laboratory-based spectroscopic reflectometry in the extreme ultraviolet (EUV). EUV reflectivity spectra of nanoscale gratings under grazing incidence illumination and their dependency on the geometrical grating parameters are discussed. A laboratory-based setup to measure such spectra is introduced and its main features are presented. A nanoscale grating with a grating period below 100 nm, consisting of multiple nanometer-size layers of materials, is experimentally investigated in the setup. The experimental results are consequently compared to a rigorous model fit of the reflectivity and thus the ability to model the grating’s interaction with EUV radiation is shown.

In recent years, miniaturization and multilayering have been key technologies in order to improve performance and integration of semiconductor devices. For a fine dimension control of semiconductor devices, the critical-dimension scanning electron microscope (CD-SEM) has been widely used. In addition to this technique, the recent advent of 3D semiconductor devices has created a strong demand for new dimension control method. We have developed a scanning ion microscope with a gas field ion source (GFIS-SIM) to meet this demand. The GFIS has almost the same brightness as a field emission type electron source, and it is possible to switch from a light-element ion used for observation to a heavy-element ion used for processing. In this way, we can achieve a high degree of freedom in the sample chamber (regarding sample size and inclination), an observation resolution of better than 1 nm, and the sample processing function with one identical ion source and beam column. We succeeded in observing the internal structure of several samples using this technique. We dug each sample with 2 kV neon ions to expose the internal structure, switched the ion beam, and successfully observed its internal structure with a hydrogen ion beam of 30 kV.

Microscopically, a rough edge can be considered as a set of exclusions (i.e., bumps) and inclusions (i.e., divots) along a sidewall. These local perturbations along the sidewall can be thought of as the most basic building blocks of the geometry of rough edges. However, these two structural geometries image differently under critical dimension scanning electron microscopes (CD-SEM), and also when scanned from different directions. An understanding of these imaging differences should be important to improving roughness measurement accuracy. In this work, images from using Monte Carlo and analytical simulations of different sizes of exclusions and inclusions on flat edges are used to better understand the effects of the local microgeometry of the edge, and also how various SEM algorithm choices, parameters, beam size/shape, charging, scan direction, and pixel size/scanning scheme influence SEM line edge uncertainties for such features. Furthermore, how these errors interact with roughness power spectral density (PSD) metrics will be explored, imparting knowledge for optimizing roughness PSD measurement with minimized error.

Deep Learning (DL) techniques based on Denoising Convolutional Neural Networks (DeCNN) are applied in the denoising of SEM images of line patterns to contribute to noise-reduced (unbiased) LER nanometrology. The models of DeCNN are trained in a sufficiently large set of synthesized SEM images with controlled Gaussian and Poisson noise level. Due to the image-based nature of the DL approach, it can be combined sequentially with the state of the art PSD-based method especially for highly noisy images where the use of the PSD-based method alone fails. The results for test synthesized images show the high predicting capability of the DL assisted method for the commonly used LER parameters and functions (Rms, ξ, α, PSD) of the true (zero-noise) values revealing its potential for future use toward an unbiased LER metrology.

The use of large numerical apertures in spectroscopic ellipsometer (SE) or reflectometer (SR) designs allows for smaller measurement targets, but it may introduce side effects like the propagation of high diffraction orders into the collection pupil. In the normal optical critical dimension (CD) measurement condition, the zeroth-order diffracted light is the only light illuminating the pupil. However, when the pitch of the measurement target is large enough, the high-order diffracted light can also enter the pupil and mix with the zeroth-order diffracted light. This contaminates the measurement and leads to inaccuracies in fitting the target's model to the data.

In this paper, we propose a method that retains good measurement results even when the collected spectrum includes contamination due to high-order diffraction. In this approach, we treat the high-order diffracted light contamination as the primary source of error in the measurement. We modify the maximum likelihood estimation using one of three different additional weighting schemes that lead to optimal measurement results. In general, we have found that not all the wavelengths in the affected wavelength zone have the same contamination impact

. The above concept was validated using a synthetic and an actual large pitch CD measurement, successfully demonstrating that the proposed method virtually eliminates the inaccuracy. These results show that this method effectively allows the user to use the full wavelength range of interest from 190-800nm, in spite of the fact that a significant fraction of this wavelength range includes the presence of higher diffraction orders. This method thus allows for accurate measurements of large pitch SRAM targets and enables yield improvement for N5 and newer logic devices.

We have been integrating an automatic aberration correction system, capable of chromatic and spherical aberration correction, to an SEM platform. Performance in CD metrology and inspection are being evaluated at ultra-low landing energy conditions down to 100 eV. The improvement in image sharpness was proved with Au particle samples. Furthermore, the surface sensitivity and image sharpness, during SEM observation of devices consisting of light elements, were also improved. Both the bridge structures of the DSA fingerprint pattern, and the unevenness of the outmost surface of FinFET gates were clearly observed at landing energy of 150 eV. Besides, line-edge roughness and subtle residue at trench area of EUV resist L&S pattern was also clearly observed at landing energy of less than 100 eV, which indicates aberration-correction-technology integrated SEM is promising for both inspection and CD metrology in the EUV lithography era.

In semiconductor industry, as physical sizes of integrated circuit (IC) components continue to shrink, critical dimension (CD) metrology plays an important role in manufacturing process monitor and control. However, when prior knowledge of E-beam tool conditions and statistics of underlying imaging samples are limited or missing, metrology parameters (such as imaging conditions and CD measurement parameters) are often selected empirically and not optimized in terms of measurement accuracy or precision. Common practice involved in fine-tuning some of the parameters may result in a time-consuming trial-and-error cycle.

In this paper, we propose a guidance system to provide an optimized set of metrology parameters given a line/space pattern image or images of scanning electron microscope (SEM). The proposed system models input condition with a comprehensive set of model parameters and then statistical analysis is done based on modeling outputs. A set of metrology guidelines, such as measurement parameters and achievable precisions, can be recommended by the proposed system. The validity of our method has been demonstrated by comparing the recommended parameters with the optimal parameters found by brute-force search on a set of 100 SEM images of line/space patterns.

Metrology of 3D NAND device architecture is challenging due to structural complexity, low signal to noise and contrast to noise ratio in the electron micrographs. Efficient, automated tools that can measure critical dimensions of 3D NAND in electron micrographs can be a part of solution for process monitoring, uniformity control and structural modelling through OCD, CD-SEM, e-beam tech., etc. In this paper we present an automated technique based on a snake algorithm in a multi-stage, scale-space framework to delineate continuous interfaces between different materials/layers of 3D NAND cells. The snake algorithm takes an initial contour and forces the initial contours to move and deform towards the interface between different material layers using an iterative energy minimization process while preserving the continuity and smoothness of the contour. At the end of energy minimization, the interface between different materials such as central hole, core silicon oxide, poly silicon, tunneling silicon oxide, silicon nitride with storage function, blocking silicon oxide, outer metal layers, etc., are delineated and marked by labelled contours. Prior knowledge, if available, about the number of material-layers and approximate distance between them can be used to improve the efficiency of the process. The proposed method transforms the micrograph into a digital metrology image where critical dimensions such as thickness of the materials, shape of the material layers, etc., can be automatically measured. The additional information provided by continuous contours can be used with ‘Big Data’ analytics to uncover patterns, variations, and outliers that may go unnoticed in discrete measurement data.

We propose a novel combined measurement system for measuring surface and thickness profiles of multi-layered film specimens named as MYFIELM (Measurement sYstem of Film structure by Interferometry and ELlipsoMetry). Film thickness profiles measured by ellipsometry mode are transferred to interferometry mode in MYFIELM and the surface profile can be extracted from the spectral phase of the interferometry containing both of surface height and film thicknesses. For the verification, each performance of the operating mode was confirmed and 4 film layered specimen was measured in comparison of the reference values. To the best of our knowledge, MYFIELM is the most suitable solution for characterizing thin film structures with a textured substrate without any damage on the specimen compared with the previous techniques even though it needs further improvements for stability and reliability.

As semiconductor technology nodes keep shrinking, ever-tightening on-product overlay (OPO) budgets coupled with continuous process development and improvement make it critical to have a robust and accurate metrology setup. Process monitoring and control is becoming increasingly important to achieve high yield production. In recently introduced advanced overlay (OVL) systems, a supercontinuum laser source is applied to facilitate the collection of overlay spectra to increase measurement stability. In this paper, an analysis methodology has been proposed to couple the measured overlay spectra with overlay simulation to extract exact process information from overlay spectra. This paper demonstrates the ability to use overlay spectra to capture and quantify process variation, which in turn can be used to calibrate the simulation stacks used to create the SCOL (scatterometry-based overlay) and AIM overlay metrology targets, and can be fed into the fab for process monitoring and improvement.

Atomic Force Microscopy (AFM) is a capable to provide high resolution CD-metrology and precise defects analysis on large wafers, masks or displays. However, AFM is not enough productive for high-throughput industrial uses. Standard single probe AFMs are showing low throughput as a serial imaging tools. The use of an array of four cantilevers as a Quattro-Array results in effective speed of 6 to 10 mm/s. An image size of 0.5mm x 0.2mm is achieved employing a piezoelectric positioner with a scan range of 200μm x 200μm and a resolution of 0.25nm (x,y) and 0.2nm (z), respectively. These capabilities are qualifying the Quattro-cantilever array system as fastest tool for. In this paper we present new results obtained with our Quattro-AFM high-throughput parallel SPM system that exhibits two key advances that are required for a successful deployment of SPM in time-efficient metrology, defect analysis and mask inspection.

Requirements of surface quality of silicon wafer are increasingly restrict. Many investigations have been done to inspect defects on silicon wafer. However, rare studies have been reported on defect components inspection which is also critical to trace to the source of defects and monitor the manufacture processes in time. In order to inspect the components of contaminated particles on silicon wafer, especially with a high speed and in line mode, dual nanosecond pulse laser system both wavelengths at 532nm is designed in which one laser pumps the particles away from wafer surface almost without damage, the other laser breakdowns the particles in air above the wafer surface to obtain the emission lines of the contaminated particles by a spectroscopy with CCD. The sensitivity of the dual pulse laser system is evaluated.

Line edge roughness (LER) measurement is one of the metrology challenges for 3D device structures, and LER reference metrology is important for reliable LER measurements. We developed an LER measurement technique, which is able to analyze LER distribution along height of a line pattern, with high accuracy, resolution, and reproducibility. Highly accurate atomic force microscopy (AFM) image of a vertical sidewall of a line pattern was obtained using a metrological tilting- AFM, which offers SI-traceable dimensional measurements. The tilting-tip was controlled with an inclined servo axis and scans the vertical sidewall along a line pattern with a high sampling density to enable an analysis of the LER height distribution at the sidewall. A horizontal cross-section of the sidewall shows sidewall roughness with sub-nm resolution. Power spectral density (PSD) analysis of the sidewall profile showed that the PSD noise in the high-frequency region was several orders of magnitude lower than the noise of typical scanning electron microscopy methods. AFM measurements were sequentially repeated three times to evaluate the reproducibility of the sidewall measurement and LER analysis; results indicated a high reproducibility of 0.07 nm evaluated as a standard deviation of LER at each height.

Industry standard yield models make no provision for the heterogeneity of defect density or indication of how the uncertainty of defect density is propagated to uncertainty of die per wafer yield. In this paper we show how standard models can be extended by causal analysis to improve their generality. Causal diagrams are employed to specify yield models and make their assumptions transparent. Worked examples are provided as well as all the open-source code needed for the analyses.

TNO is developing a novel Large Dynamic Range Atomic Force Microscope (LDR-AFM), primarily but not exclusively designed for sub-nm accurate overlay metrology. The LDR-AFM combines an AFM with a 6 degrees- of-freedom interferometric positioning stage, thereby enabling measurements of sub-nm features on a wafer over multiple millimeters marker-to-feature distances. The current work provides an overview of recent developments and presents the first results obtained after final integration of the complete system. This includes results on the AFM head development, the validated positioning stage performance, the first AFM images, and long-term stability measurements.

In the leading-edge production measuring the geometrical dimensions with e-beam inspection (CD-SEM data) or scatterometry technology (OCD data) is one of the most time-consuming steps without adding value to the wafer. Hence the fabs want to limit the effort to minimize the costs per wafer. On the other hand, the output of the metrology steps is needed to feed the SPC and APC systems with sufficient information. We handle that trade-off with a new sampling scheme optimizer supporting CD-SEM and OCD data.

Generally, we can use the sampling scheme optimization for a set of different features and their measured parameters in parallel. Especially in logic, but also for memory, the focus and dose dependencies of several features may be different. Hence, we optimized the distribution of the measured sites to create a perfect representation of the systematic fingerprint for all important anchor features within one single sampling scheme.

For the verification of the approach we investigated two cases. The first case are dense CD measurements, which are usually needed to create and update intra-field dose corrections. We minimize the number of measured sites significantly and distribute the remaining sites over different fields to ensure a good coverage of the systematic effects. Finally, that allows us a much higher update frequency of the dose corrections and yields in smaller CDU values.

The second case optimized the throughput of an OCD metrology system. The applied high-density sampling scheme for the focus monitoring done on reference wafers takes a lot of time during measuring. That specific type of measurement is done for monitoring and updating the focus reference corrections. With our proposed solution, we can achieve the same quality with respect to the reference measurement with more 50% less measured sites.

With the miniaturization of devices, hot spot evaluation of a wide area of a wafer for small change points such as wafer topology is required. DBM (Design Based Metrology) is an effective method for evaluating systematic defects of multiple patterning and EUV lithography. However, it takes a long time to evaluate because it is necessary to acquire a high-SN SEM image captured by low-speed SEM scanning conditions. Therefore, we developed a new pattern matching method of DBM by utilizing deep learning technology. Our proposed method can handle low-SN SEM images captured under high-speed SEM scanning conditions.

In the proposed method, we use deep learning to estimate design layout from SEM image, and then perform pattern matching between this estimated design layout and the true design layout. The proposed method is particularly effective for pattern matching of low-SN SEM images and circuit pattern distorted during manufacturing process. It is expected that this method will be advantageous for evaluating mass systematic defects during the process development. Experimental results showed that the proposed method could estimate the design layout from the low-SN SEM image and improve the pattern matching success rate.

To realize higher resolution in optical inspection systems is typically using shorter wavelengths including UV light and a higher NA of the objective lens. Extreme performances of illumination and imaging systems in well-matched situations are inevitable with further effort put on the development of an effective optical system for inspecting microscopic defects on patterned wafers.

For this study, we focus on the dark-field illumination system for index-matched near-field microscope using an aplanatic solid immersion lens (A-SIL). We present dark-field illumination that has illumination channels on the side of the A-SIL to overcome the issue of deficient space. The table-top experiments are conducted to show a feasibility of a dark-field imaging method for the near-field condition before verifying the performance of the optical system.

The introduction of advanced technology nodes in deep UV (DUV) lithography (litho), involving multiple litho steps, has tightened the wafer on-product overlay specifications [1]. The industry trend already pushes the overlay requirements to the sub-nanometer regime (and so the mask registration requirements tightens as well). In the most general view, wafer on-product overlay errors are a combination of intra-field (within field) and inter-field (field-to-field) errors. A given litho layer intra-field overlay error includes several systematic sources, such as scanner lens-to-lens residuals and mask writer residuals. Parallel to the nodes and litho techniques advancing, the ability to accurately measure overlay at high lateral resolution have being successfully introduced, both at wafer and mask side.

The recent developments in scanner technology improved the ability to control intra-field overlay at high-order across the exposure field. However, this is still in several millimeter lateral resolution control ability at its best, leaving residual errors in the sub-millimeter to few millimeter regime without the ability to further suppress them to the target specification, nevertheless, not to the sub-nanometer magnitude.

In this work, we have empirically evaluated the ZEISS state-of-the-art mask tuning solution named ForTune ERC (Enhanced Registration Control). This solution is based on laser processing of the mask bulk by the ZEISS ForTune tool. It allows to suppress few nanometer overlay residuals (post the scanner best-can-do) down to deep sub-nanometer, all even at sub-millimeter sampling resolution (x1 wafer level) and low-to-high residuals modulating frequency.

For the sake of this study, we have used a dual-image mask to form one overlay signature at wafer side. Two wafers have been exposed prior to the laser-based tuning of the mask bulk; the wafers overlay error was measured and used as an initial overlay problem to begin with. A second exposure of two additional wafers was performed post the problem-solving by the ERC model and the consequent mask laser-based tuning. The pre/post wafers were then compared to examine the improvement in overlay at wafer side. CD uniformity (CDU) data has been collected as well, to confirm no degradation in CDU due to the ForTune ERC process.

The combination of this advanced method of intra-field control with high-order correction per exposure (CPE) by the scanner, provides an efficient co-optimized solution to tightly control the overlay of existing and future nodes at DUV litho.

Metrology and inspection (MI) processes are established at critical points of the semiconductor manufacturing process in order to maintain a certain yield and also provide information needed for future processes improvements. Typically, the inspection consists of dark-field (DF) inspection and SEM review/classification processes. An optical DF microscopy system (or inspection tool) first detects particles or pattern defects on wafers and obtains their position coordinates. However, due to its limited optical resolution, the DF system is not widely applied in the review process, which requires higher resolution images of the detected defects such as those provided by scanning electron microscopy (SEM) but with a sacrifice of throughput. We propose an innovative idea of applying two (or three) dark-field microscopy images for intermediate defect classification and size estimation under optical resolution. The proposed method utilizes the angular scattering distribution from a defect that is in the Mie scattering domain, which varies depending on both the beam and defect properties (wavelength, polarization, incident angle; shape, size, complex refractive index). It captures three darkfield images of the same wafer by three inter-changeable objectives with different magnification and numerical aperture (NA) values under identical side illumination conditions. We estimate the defect types and sizes simply by investing three measurements. We demonstrated this proposed method to classify and estimate the defect size down to ~ 80nm by an existing UV inspection tool with three DF imaging modes; 1) M15 mode, sampling stance = 150 nm, NA =0.6, 2) M25 mode, sampling distance = 250 nm, NA=0.36, and 3) M40 mode, sampling distance =400 nm, and NA =0.23. We demonstrated its feasibility by an independent SEM measurement of the detected defects.

To produce high-yielding wafers, overlay control in DRAM production needs to be exceptionally tight. The ASML YieldStar 375F introduces a continuous wavelength source and dual wavelength operation to deliver the high measurement accuracy and robustness required as input to the overlay control loop. At the same time, the high throughput required to allow high sampling densities is maintained. The YieldStar 375 was evaluated and adopted for Samsung’s D1y DRAM node.

It is important to remove image noise properly to measure critical dimension (CD) and roughness values from scanning electron microscope (SEM) images. In order to reduce image noise, the number of electron beam (EB) scans, or frame number, is increased. However, this excess EB irradiation damages the objects being measured and changes their size. In this paper, a new image analysis method is introduced to remove image noise without a typical noise filter. In this method, each image frame is used in a four dimensional array, and several artificial images are generated and edge coordinates are calculated. As a result of this new method, we can separate the line width roughness (LWR) components into process roughness and image noise, and analyze images with lower number of frames with minimal EB damage.

The impact of image noise on the accuracy of CD extraction is explained in the section on analysis of variance (ANOVA). The variation is separated as wafer to wafer (WTW), field to field (FTF), die to die (DTD), pattern to pattern (PTP), line width roughness (LWR), and stochastic pattern noise (SPN; which is random variation per a pattern) at this ANOVA. Roughness component from image noise is included in SPN. It is possible to remove the image noise component from SPN by applying this new image analysis method, and it is also possible to discuss the SPN from shot noise of exposure tool or variation of resist material component. ANOVA can put an end to discussion of measurement length of line pattern to know the state of low frequency roughness. LWR component of long wavelength is distributed to PTP and SPN when short patterns are measured. It is important to remove image nose properly and to compare the statistical analysis processed SPN value.

There are different approaches for alignment sampling optimization. In order to determine, which approach is optimal, OPAL run-to-run simulations¹ must be executed using the result of the different sampling optimization. This means that there is a two-step approach: first, an iterative sampling optimization algorithm that results in optimal overlay modeling. Then, a run-to-run simulation is done to verify the impact on the overlay performance.

In this study, we investigate on the behavior of four different approaches to alignment sampling optimization on four different layers and analyze which approach is most suitable for which layer.

In leading edge lithography, overlay is usually controlled by feedback based on measurements on overlay targets, which are located between the dies. These measurements are done directly after developing the wafer. However, it is well-known that the measurement on the overlay marks does not always represent the actual device overlay correctly. This can be due to different factors, including mask writing errors, target-to-device differences and non-litho processing effects, for instance by the etch process.¹

In order to verify these differences, overlay measurements are regularly done after the final etch process. These post-etch overlay measurements can be performed by using the same overlay targets used in post-litho overlay measurement or other targets. Alternatively, they can be in-device measurements using electron beam measurement tools (for instance CD-SEM). The difference is calculated between the standard post-litho measurement and the post-etch measurement. The calculation result is known as litho-etch overlay bias.

This study focuses on the feasibility of post-etch overlay measurement run-to-run (R2R) feedback instead of post-lithography R2R feedback correction. It is known that the post-litho processes have strong non-linear influences on the in-device overlay signature and, hence, on the final overlay budget. A post-etch based R2R correction is able to mitigate such influences.²

This paper addresses several questions and challenges related to post-etch overlay measurement with respect to R2R feedback control. The behavior of the overlay targets in the scribe-line is compared to the overlay behavior of device structures. The influence of different measurement methodologies (optical image-based overlay vs. electron microscope overlay measurement) was evaluated. Scribe-line standard overlay targets will be measured with electron microscope measurement. In addition, the influence of the intra-field location of the targets on device-to-target shifts was evaluated.

Every nanometer of residual nano-topography (with high spatial frequency fingerprint) that the scanner cannot correct during the wafer exposure directly propagates into the focus budget [1].

Process windows are getting tight with a greater and greater contribution of the focus budget. Nanotopography is highly correlated to the chip layout. As a consequence it shows systematic peaks and valleys shifting locally optimum process conditions. Mean, standard deviations and ranges are not enough to characterize it.

It is of high importance to know topography maps to identify care areas on silicon with high risks of defocus situations [2]. These maps can be measured at any process step using PWG (Patterned Wafer Geometry) tools but could also be predicted with models (see proof of concept [3]).

The first part of this paper deals with the development of scripts to extract and express in multiples ways topography information. Different types of expressions will be shown followed by two use cases related to topography description situation: striation detection and slurry choice for CMP. Those two use cases are proofs of concepts showing that data valorization is a path to provide information that can help process engineers to make decisions and save time for defect detection.

This paper ends with a deeper exploration of the correlations between chip designs and nanotopography from an image processing point of view (design layout and wafer topography maps). Short-range and long-range contributions of layouts are used to model nano-topography through a multiple linear regression [4] of the pre-processed design layers densities (surface and perimeter) and wafer topography which is characterized in this work using KLA PWG tooling. The goal being here to predict wafer topography before silicon is being processed so that mitigation solutions can be set up.

PWG metrology tool can measure a full wafer nano-topography map with pixels size of 100μm*100μm which is enough for a focus analysis. Results show that the first model version reaches encouraging figures of 0.77 R² for a product layer having a 20nm topography range.

The growing demand for advanced DRAM technologies requires development of novel process control methodologies reflecting design rule shrinkage. The new challenges for CD SEM metrology of dense feature arrays of DRAM layers are widely considered in the literature and ITRS documents. In addition to traditional SEM metrology methods based on measurement of individual features, the development of novel measurement techniques is required for dense cell arrays at small nodes.[1-3] We considered a novel metrology of CDSEM Critical Dimension (CD) in dense arrays, formed as capacitors in advanced dynamic random-access memory (DRAM) layers. The proposed approach is based on traditional CDSEM metrology methodology with new developments providing flexibility, CD-style high precision, and large statistical sampling capabilities for advanced Statistical Process Control (SPC). The metrology challenge is solved through development of new algorithmic approaches for dense array measurements. The approach was validated on data simulation of extracting geometry (CD) parameters of actual DRAM cell structures and verified on real data.

It was proven that higher order intra-field alignment data modeling and correction has the potential to improve overlay performance by correcting reticle heating and lens heating effects intra-wafer and wafer- to-wafer.¹ But there were also challenges shown that needed further investigation. As the alignment measurement is done on a coordinate system with absolute positions, the modeled iHOPC values might be high. A suitable method needs to be developed to distinguish between tool-to-tool offsets, process influence and layer-to-layer tool stack effect. In this paper we will take the next step and evaluate the overlay improvement potential by using intra-field alignment data in an overlay feed-forward simulation. An overlay run-to-run simulation is afterwards performed to estimate the optimization potential. To simulate higher order intra-field overlay, dense alignment data is needed. Facing the challenge of optimizing the number of measured marks but not losing relevant information, an intra-field alignment mark sampling optimization is done to find the best compromise between throughput and overlay accuracy.

The uncertainty of measurements is an important element of the measurement result. The component part of the uncertainty budget is the sensitivity coefficients included in the measurement equation that are the ratio of change in measurands to the change in each of the parameters included in the measurement equation. The use of software in the systems for measurement and modeling of measuring processes allows to take into account and analyze all possible factors of influence on the result of measurements, carry out model research, reject factors with minimal impact and vice versa, analyze in more detail those with maximum impact on expanded uncertainty.

The study of the national measurement standards allows to carry out experimental programs on their improvement and increasing the level of metrological services. The analysis of the influence of additional input quantities complicates the model equation but leads to in-depth study of the physical process. Calculations are made using the finite element method implemented in the academic version of the software package of engineering analysis.

The purpose of the work is to study the influence of additional sensitivity coefficients included in the uncertainty budget of the measurement result. In the example of modeling of the hardness measurement on the Rockwell and Super- Rockwell scales, an approach to refine the model equation based on the inclusion of additional input quantities is considered.

As a practical application, the proposed methodology is useful in evaluating the results of international comparisons. As a promising area for further research, there is an in-depth study of additional sensitivity coefficients when drawing-up the uncertainty budget on the Vickers and Brinell scales.

Each of six scanning transmission electron microscope (STEM) system alignments were characterized with a sensitivity test to better understand the impact of the alignment on microscope automation for acquisition and metrology. The upper and lower limits of the alignment sensitivity combined with the accuracy of the automated system alignments are used to determine the process capability index (C_pk). The primary limiting factor for the alignment sensitivity was passing the metrology dynamic precision criteria of <0.3nm. Strong alignment offset showed impact on the autofunction robustness, but was marginal in comparison to the metrology sensitivity. All six of the STEM system alignments resulted in C_pk values greater than 1.3, supporting a three sigma quality process. Based on these results, criteria can be defined for alignment offset limits that will trigger automated preventative maintenance (APM) re-alignments and ensure that automated STEM metrology will meet the accuracy and precision requirements for adequate process control.

As device size continues to shrink, stochastic-induced roughness of resist features exposed by photolithography is of increasing concern to the semiconductor industry. In this paper, we propose an end-to-end approach for line roughness analysis by using the Line Roughness Module from our CDU solution family, which is a part of HMI’s metrology SEM tool the eP5. Simulated Scanning Electron Microscope (SEM) images of line/space patterns are used to verify the ability of the Module to reliably extract roughness related metrics. A set of imec EUV ADI images collected on our metrology SEM tool are analyzed by the Line Roughness Module, and wafer signature maps of various roughness metrics are obtained. These wafer maps not only help to analyze different roughness contribution sources, but also provide insights about feature roughness in a systematic way. Such information can be further used in a feedback loop to the scanner for model correction and process control.

As well known that, the critical dimension continues to shrink and the overlay control appears to become much more challenging than before. In such situation, we are seeking for solutions to minimize the impact of measurement shift in overlay detection induced by process variations. When the accuracy of overlay measurement improved, corrections can be performed effectively according to the feedbacks from metrology results. We build a physical model for simulating overlay metrology employing diffraction based overlay (DBO) principles, which can help to conduct researches on DBO metrology in advanced semiconductor nodes.

In this paper, we present a physical model of the DBO metrology which based on the Finite-Difference Time-Domain (FDTD) method. The basis and principles of model establishment was discussed. After adjusting the model parameters compatible with the actual measurement conditions, the metrology wavelengths which provide the best accuracy and robustness of DBO measurement can be selected through simulations. The results of our study will be demonstrated in this publication.

The use of the finite element method in engineering calculations almost always brings some simplification in relation to the real object. Since the finite element method is a numerical method, the accuracy of the results obtained depends on the type, size and location of finite elements. In the general case, the use of models with a large mesh gives understated results. Reducing the size of an element provides the required refining of the calculation model and obtaining results that are more reliable. However, the use of finite elements of a higher order does not always lead to an increase in the accuracy of the results obtained, and in some cases, it is irrational.

An important element in the application of modern engineering software packages for solving metrological problems (modeling of measurement processes, calculations of the characteristics of components of the national measurement standards) is the reliability of the results obtained, the adjustment of the results obtained with the results got by analytical calculation with the use of classical equations (the explicit solution).

The purpose of the work is to confirm the reliability of calculations of finite element modeling in the study of the distribution of temperature field through the composition panel. Calculations are made using the academic version of the software package of engineering analysis and by the classical matrix algebra method for solving temperature problems. Based on the obtained results, conclusions are made regarding the reliability of finite element modeling data.

In this paper we propose the implementation of a machine learning technique based on Hidden Markov Models (HMMs) to provide denoising of line edges and unbiased LER measurement. HMMs are widely used with great success in speech recognition and image processing for denoising and filtering noise. Here HMMs are used for similar purposes, working with the observed (noisy) edge data, acquired through SEM imaging and an edge detection algorithm in an effort to retrieve a parent edge signal that is statistically close to the real one.

The developed HMM method was trained with the assistance of synthesized rough edges, on a wide spectrum of predefined and controlled noise levels and roughness characteristics. This ensures the method adapts on a variety of LER parameters and noise levels. The edges were then used to validate its effectiveness in a broad range of line patterns. Our results so far specify the characteristics of the training data set which are required to make the method effective in the unbiased LER measurement.

As technology nodes advance, the need for higher sensitivity optical inspection to identify critical defects has become extremely important for technology development. However, more sensitive optical inspection can induce more nuisance and hence more SEM non-visual (SNV) defects during review sampling. High SNV in the defect Pareto hinders the ability to get a true picture of the actual distribution of defect types on a wafer, and defect-of-interest (DOI) types that are crucial for process diagnostics can be missed. The culprit of this problem is the method of review sampling.

Traditional review sampling consists of two parts: binning and defect selection. Binning is defined as a set of rules and conditions determined by human experience and judgment to categorize different DOI types. Then, defects are selected from each bin and reviewed by SEM. Due to the nature of high SNV from optical inspection, the random selection of defects will end up with high SNV in the defect Pareto. A defect Pareto with high SNV provides little value to yield learning. Because SEM review plus classification is limited by time and economic budget, improving the ability to predict whether a defect is DOI or SNV before SEM review is valuable.

This paper introduces a machine learning based method suitable for high volume manufacturing that can increase the probability of finding DOIs during review sampling by integrating all available data sources, such as historical defect attributes from optical inspection, context information of the inspection recipe, design hotspots and metrology measurements. In addition to review sampling, this paper also illustrates other applications based on machine learning defect prediction, such as virtual process window discovery, and predicted defect types for trend monitoring. A predictive analytics platform was employed to allow defect type prediction based upon multiple inputs.

We have demonstrated the successful operation of a multi-beam scanning electron microscope with 331 electron beams for the first time. This makes it the world’s fastest SEM. The underlying architecture of the existing multi-beam mSEM technology fully supports the scale-up of the number of electron beams to 331. Scaling beyond this number is feasible.

This paper, originally published on 26 March 2019, was replaced with a corrected/revised version on 25 June 2019. If you downloaded the original PDF but are unable to access the revision, please contact SPIE Digital Library Customer Service for assistance.