This PDF file contains the front matter associated with SPIE Proceedings Volume 11613, including the Title Page, Copyright information, and Table of Contents.

Market forces have compressed the various node transition phases in the semiconductor supply chain – Pathfinding, Ramp, and HVM. In addition to time pressures, there are competing demands for architectural tradeoffs, novel applications, and emerging imperatives like Machine Learning (ML) and Cloud-readiness. To tackle these multi-front challenges, today’s Computational Lithography EDA solution needs to be a multi-component offering that fosters a closed loop, system-wide optimization for each phase, while allowing customizations to satisfy the requirements of the different phases. In this talk, we identify the essential components of such an EDA solution as: Predictive model, Multi-constrained, globally-aware correction scheme, Stochastic awareness, Curvilinear mask-fracture awareness, and All embedded in a Cloud-ready, ML-enabled, flexible platform. We show how these components support the competing demands for the various phases in the semiconductor manufacturing lifecycle.

Optical exposure technology has seen huge advances in semiconductor lithography applications in the past 40 years. We have seen the use of optics to create structures at the sub-10nm level by interaction with photoresist chemistry and projection optics. However, where there used to be a multitude of technology options for semiconductor technology nodes, there is now only a limited set of options. EUV is now in the mainstream for the most advanced chip nodes, supplemented with 193nm exposure tools. At the same time, there is an evolution and almost a Cambrian explosion of related technology that also requires similar precision optical tooling. The ever expanding list of these emerging technologies includes new 3D semiconductor designs, IoT, Artificial Intelligence chips, Heterogeneous packaging, MEMs, biosensors, and security applications. It seems to be natural to ask, “Is there any room for more optical exposure tools? “ This presentation will attempt to answer that question. We look at the definition of optical exposure technology and what it means for the wide range of applications from semiconductor to the aviation industry. We present Nikon’s recent excursions with new products and show concepts in possible technology not only for advanced semiconductors nodes but also for large field high resolution applications such as augmented reality. Finally, we describe our recent developments in optical Maskless technology.

As the design layout of integrated circuits (ICs) is continually scaling down, sub-resolution assist features (SRAF) have been extensively used in resolution enhancement technique (RET) applications to enhance lithography printing fidelity and widen the manufacturing process window (PW). With conventional SRAF insertion techniques, rule-based SRAF (RB-SRAF) and model-based SRAF (MB-SRAF) methods have been widely adopted. The typical RB-SRAF is an efficient method to generate SRAFs consistently for simple designs, but cannot be optimized for multiple critical patterns or complex layout schemes. Although MB-SRAF is able to achieve better process window as well as reducing conflicts between placement rules and clean-up rules, many iterations for convergence and extremely high computational costs are required. The explosion of machine learning techniques could facilitate the complex processes of mask optimization, such as SRAF insertion. In this paper, generative adversarial network was studied on a Via layer of advanced 3D NAND flash memory, by training target images and Inverse Lithography Technology (ILT) images of target patterns. GAN models, pix2pix and CycleGAN, were first trained and then utilized to synthesize realistic ILT images. These ILT images were eventually translated to polygons of SRAF with simplification process and mask manufacturing rules check (MRC) constraints. The simulation results demonstrate that CycleGAN approach can place SRAF with comparable performance to mask optimization (MO) result which was optimized by the Tachyon Source-Mask Optimizer (SMO). Most importantly, the efficiency of SRAF insertion can be enhanced significantly through the generative adversarial network.

Fast computation of process variation band (PVB) is critical for several lithography applications such as yield estimation, hotspot detection, mask optimization, and etc. Conventionally, PVB is computed by lithography simulation that is very slow and can only be applied for a small part of a chip. These small parts of a chip are identified through a pattern matching process, where unseen patterns are often missed. We explore conditional generative adversarial networks (cGANs), a couple of machine learning models, for predicting PVB with high speed and sufficient accuracy. In our proposed method, we divide a full-chip into several small clips and then predict PVB for a small region of interest at the center of each clip. Experiments show that our proposed method can successfully predict PVB for more than 98% of the patterns with an average accuracy, and speedup of 86%, and 500 times, respectively, compared to the rigorous lithography simulation.

Data sampling is a corner stone in any machine learning applications, and ML-OPC is no different. As feature resolution and process variations continue to shrink for new nodes of both DUV and EUV lithography, the amount of data that can be collected can be enormous, and smart advanced data sampling will be indeed needed. In last year’s SPIE paper in Refs. 1, we explored how can we utilize parametric test patterns to augment random sampling to collect an improved training data set. Given that random sampling has been good enough for some older technology nodes, a new advanced way to sample the data became inevitable for newer nodes. In this paper, we explore a few techniques to improve the quality of the ML-OPC training data. We show how different sampling methodologies can affect the training and inference results. We start by exploring different techniques then compare the results of different sampling techniques using both geometrical and image parameters and compare to regular random sampling results. We will also show how the Proteus capsules made this work easy and accessible for the user. At the end, we will show how this work can be integrated in one Proteus Workflow (PWF) for easier exploration for the results.

Semiconductor manufacturing equipment must maintain high productivity and provide high-yield processing and Canon has developing high-reliability exposure tools that have demonstrated high-uptime and performance stability in production. As global emergency epidemic restrictions limit the travel of expert engineers, customer service becomes more challenging and alternative methods of support are being developed to help customers meet their production roadmaps. To help control performance, lithography tools have sophisticated logging systems that can monitor every movement in the tool and we studied a novel Artificial Intelligence system that utilizes big logging data to help improve exposure tool uptime, productivity and performance related to yield. One goal of our study is to minimize exposure tool downtime by monitoring and reacting to tool status. For this purpose we are applying machine learning to develop abnormality detection or prediction models with automated recovery procedures for each abnormality. We will report on Auto-Fault-Tree-Analysis (FTA) models being constructed to evaluate large volumes of design and trouble information to help minimize downtime. Another study goal is to improve lithography tool performance by monitoring and reacting to factors including overlay accuracy and CD uniformity that can strongly affect device yield. Outputs of this analysis include simulation and optimization of equipment performance, and virtual metrology. This paper reports on the system we are developing to help increase the uptime, productivity and imaging performance of Canon semiconductor lithography tools. The system is designed to monitor the operating state of lithography tools and apply automated recovery and optimization actions identified through machine learning.

Digital Scanner (DS), a DUV optical maskless exposure tool is being developed. It uses a micromirror-type spatial light modulator (SLM) to create the “mask” pattern combined with a solid state laser with wavelength of 193 or 248 nm. The exposure concept of DS and advantage of solid state laser as an exposure light source is described. DS proof-of-concept tool with resolution of half-pitch 80 nm L/S was developed. The exposure results of maskless unique application such as large area printing and chip ID printing for security purposes are shown.

A New Generation Cost-efficient Laser Mask Writer for Mature Semiconductor Nodes Mycronic introduces SLX series – a new generation cost-efficient laser mask writer – to meet the ever increasing demand for laser based photomask writer driven by new semiconductor trends such as “More than Moore” and “Electronification of everything”. Photomasks of mature design nodes are required due to large variety of designs combined with price-sensitive low volume manufacturing. In this paper, Mycronic shares key technologies used in SLX series and how to achieve the cost effective mask manufacturing and demonstrates the superiority of the system by trecent evaluation data.

Inverse Lithography Technology OPC (ILT) is going to play a critical role in addressing challenges of optical and EUV lithography as industry pushes towards advanced nodes. One major barrier in adoption of ILT was mask writer’s inability to efficiently write curvilinear patterns. With the introduction of multi-beam mask writers [1] [2], this barrier has been removed and widespread adoption of ILT is imminent. Traditionally, mask writers have accepted only trapezoidal inputs to the tool, though recent trends show that mask writers are adopting to newer formats which already reduce file size. However, as the ILT shape complexity and data volume increases further for 5nm nodes and beyond, the explosion of mask pattern data file size becomes a major concern. Therefore, there is a need for the industry to look towards other compact formats of data representation that will be capable of serving well for multiple generations of mask making. In this paper we will be comparing various curvilinear data representation schemes and their value in the curvilinear ILT based mask manufacturing flow. We will demonstrate that given the nature of curvilinear data, representing it using native curve formats has lot of value in terms of file size reduction for futuristic mask making flows. Same format may not be applicable for all type of features in the input mask. These options will be discussed. There is also a need to compare the value of such exotic representations with regular simplification approaches that reduce data volume using standard methods. We will make that comparison in the paper and discuss the extents/limits of all these techniques. Comparison of changes in simulated mask contours and wafer contours will also be made.

More-than-Moore approaches to improve system performance have been a hot topic for a more than a decade as a way to maximize the efficiency and increase the bandwidth of high performance computing systems. Fan-Out packaging that realizes submicron Redistribution Lines (RDL) and large die sizes is one technology that can help enable complex heterogeneous integration for applications including Artificial Intelligence (AI) and autonomous driving. For systems requiring large package sizes, Panel Level Packaging (PLP) can offer efficiency and cost advantages over Wafer Level Packaging (WLP). PLP however poses unique technical challenges including the requirement to realize uniform submicron patterning across the entire rectangular panel. To meet this challenge, Canon developed the first patterning exposure tool (stepper) capable of submicron resolution on 500 mm panels. The panel exposure tool is equipped with wide-field projection optics that offer a large 52 mm × 68 mm image field and a 0.24 NA that is optimum for submicron resolution. The stepper also features an updated panel handling system for processing up to 515 × 515 mm panels. In this paper, we will report on our study of fine patterning on rectangular panels using the submicron resolution panel stepper and will introduce technology innovations supporting advanced heterogeneous integration. Our study researched photoresist material performance and slit-coating uniformity challenges we identified through collaboration with resist vendors and slit-coating equipment manufacturers. We will report on the results of our collaborative study and will discuss current and future PLP advantages, challenges and solutions.

Chipmakers have used cross-platform of both EUV exposure and ArF immersion multi-patterning exposure depending on cost effectiveness at each layer.　 ArF immersion exposure has been required lower linewidth roughness(LWR) to reduce cross matched machine overlay(xMMO) which is the overlay between the different platforms. ArF light sources essentially produce speckle as non-uniform intensity distribution resulting from interference effects generated within a beam. It leads to increase LWR, which results in increasing xMMO. The latest ArF immersion light source, GT66A is introduced a new optical pulse stretcher(OPS) that increases pulse duration to reduce speckle by 30% to improves LWR, which reduces xMMO. This technology will improve chip yield for chipmakers in the processes mixed ArF immersion exposure and EUV exposure.

Over the years, lithography engineers have continued to focus on CD control, overlay and process capability to meet node requirements for yield and device performance. Previous work by Fukuda1 developed a multi-exposure technique at multi-focus positions to image contact holes with adequate DOF. Lalovic2 demonstrated a fixed 2-wavelength technique to improve DOF called RELAX. The concept of multi-focal imaging (MFI) was introduced3 demonstrating two focal positions are created that are averaged over the exposure field, this wavelength “dithering” approach which can be turned on and off, thus eliminating any potential scanner calibration issues. In this work, the application of this imaging method (1 exposure-2 focus positions) can be used in thick photoresist and high aspect ratio applications. An example of thick photoresist imaging is shown in figure 1. We demonstrate 5um line and space features in 10um of photoresist at 3 different imaging conditions. On the left, single focus imaging (SFI) at best dose and focus, the center image which is also SFI but at a defocus of +3.2um. On the right is MFI with 2 focus positions of 0 and 2.8um. Here we can see a significant improvement in the SWA linearity and image profile quality. A second example of high aspect ratio imaging using MFI is shown in figure 2. The aspect ratio of 13:1 is shown for this. The use of Tachyon KrF MFI source – mask optimization flow will be reviewed to demonstrate optimum conditions to achieve Customer required imaging to meet specific layer requirements.

PTD photoresists are still the main type of photoresists used for tight pitch layers in advanced patterning. Recent experimental results show evidence that the same mechanical deformation behaviors seen in NTD photoresist process also exist in PTD photoresist processes. These PTD photoresist deformation behaviors cause CD differences which significantly impact CD control budgets in modern technology nodes. Therefore, there is a strong need to accurately model PTD photoresist deformation effects in compact OPC models. In this paper we discuss the polymer physics relevant to physical deformation in PTD photoresists in comparison to NTD photoresists

Computational lithography applications for OPC/ RET utilize models that represent the lithographic process in simulations. The quality of OPC/ RET wafer results strongly depends on the quality of the model. Hence, achieving model quality and experimental match is the goal of the model calibration process where models are calibrated to experimental data. Ideally, the model would be calibrated and validated to a data set that completely covers the entire design space and all process conditions. A promising alternative to the traditionally applied SEM-CD-based model calibration is the calibration to pattern contours directly with benefits in design space coverage, reduced metrology effort and data preparation complexity. However, contour calibration also demands a new standard operating procedure for contour specific metrology, pattern design and calibration. Goal of this work is to develop and exercise a full contour-based calibration methodology. Firstly, we discuss preconditions for a successful calibration: good quality contour input data, predictive modeling of optics, mask topography and 3D resist and additional calibrator functionality to include aspects of alignment and pattern specific measurement confidence. Secondly, we assess pattern for their calibration-suitability using a metric for pattern information density. Experiments are performed to show the applicability of the metric and the potential to calibrate to a minimal set of patterns. A model calibrated to a well selected single 2.25 μm² contour is predicting a large set of pattern contours, 3D resist characteristics and SEM-CD focus-exposure process windows.

The fast rigorous model (FRM) is a first principles solver based on sequential simulations of photochemical reactions in photoresists. We report the evaluation of FRM relative to compact models (CM1) for NTD OPC model accuracy. We demonstrate equivalent or better accuracy to CM1 when FRM is combined with a CM1 model of the same composition. In the case of CTR to FRM comparison, FRM is 34% more accurate in calibration and prediction on average across 20 testcases. FRM is 5% more predictive than the most complex CM1 modelform tested with similar calibration accuracy. FRM supplemented with limited CM1 terms provides better verification accuracy for SRAF printing and hotspot detection. Further, the input data needed to train the FRM model in order to achieve high predictive accuracy is a fraction (1-5%) of that needed by more complex CM1 modelforms. Finally, we show through the Akaike Information Criteria method that FRM is more predictive than an equivalent CM1 model based on the degrees of freedom in the modelform and quantity of data available.

Accurate and fast lithography model is necessary for computational lithography applications such as optical proximity correction (OPC) and lithography rule check. In lithography model, optical model calculates image intensity followed by resist model that outputs a resist contour. Resist model is an empirical model, in which images are convolved with resist kernels and their weighted sum is used to derive a resist model signal that is compared with some threshold. Conventional resist model use a simple form of resist kernels such as Gaussian kernels, therefore it requires many kernels to achieve high accuracy. We propose to use free-form resist kernels. Resist model has the same structure as convolutional neural network (CNN), thus, we represent resist model with free-form kernels in CNN and train the network. To avoid overfitting of the proposed model, we initialize the model with conventional Gaussian kernels. Training data is carefully selected so that resist contour is accurately predicted. A conventional resist model with 9 Gaussian kernels is converted into a model with 2 free-form kernels, which achieves 35% faster lithography simulation. In addition, simulation accuracy in CD is improved by 15%.

In world-leading semiconductor manufacturing, the device feature size keeps on reducing and with it processes become more challenging in the next technology node. The On Product Overlay (OPO) budget is therefore required to reduce further. Alignment is one of the key factors in reducing overlay wafer to wafer (W2W) variations. To save product area and reduce scribe line width, small alignment mark is evaluated to achieve the similar results as reference mark and to optimize the OPO performance. In this work, we will show the experimental results of small alignment mark and investigate the on product overlay performance by simulation.

Improving on product overlay is one of the key challenges when shrinking technology nodes in semiconductor manufacturing. Using information from non-lithography process steps can unleash overlay improvement potential.1 The challenge is to find intra-wafer signatures by measuring planar distortion. Several previous applications showed that using exposure tool wafer alignment data can improve overlay performance.2 With smart placement of alignment mark pairs in the X and Y direction, it is possible to determine intra-wafer distortion wafer-by-wafer. Both the measurement and modeled results are applied directly as a feed-forward correction to enable wafer level control. In this paper, the capability to do this is evaluated in a feasibility study.

In this paper we present the key enhancements incorporated in the new NXT platform and also share future development steps enabled by the platform. These innovations build on driving the system productivity while in parallel improving the overlay performance and at the same time minimizing the scanner grid differences between NXT-based ArF/ArFi/KrF and NXE-based EUV scanners. Both hardware as well as software improvements play an important role in improving cross-matching overlay performance. On the hardware side, changes have been introduced to key modules such as the projection lens and the reticle stage to better match to EUV layers. Furthermore, the new NXT platform introduces a more powerful wafer stage to support better overlay accuracy as well as improved productivity. Complementary software-based corrections are developed to further correct for grid imperfections. For instance to reduce the impact of DUV pellicle distortions, onscanner real-time corrections have been added to the scanner metrology control architecture. ‘Maximizing the number of good-wafers-per-day’ has been the guiding principle for the development of the new NXT platform. Apart from driving the scanner productivity along the traditional wafer-per-hour metric, advancements have been implemented to improve the operational efficiency of the scanner on production use-cases while also minimizing the time spent on required system maintenance. This all to maximize the effective scanner output under HVM conditions. The new NXT platform is currently being rolled out for the most advanced immersion and ArF scanners – the NXT:2050i and the NXT:1470. Going forward, it will support further productivity steps and improved overlay accuracy and EUV matching developments. The platform is also prepared to support KrF scanners in the near future, where especially the productivity will be stretched for this wavelength. Longer term this platform will serve as the stepping stone towards significantly higher wafers-per-day productivity levels and sub-nm overlay accuracy.

In the last decade, Photonics Technology has been an emerging technology for optical telecommunications and for optical interconnects in microelectronics. As a result, a large diversity of Photonics design methodologies has merged with very challenging scales and shapes. Manufacturing such curvy and critical photonics shapes requires advanced Resolution Enhancement Techniques (RET) including Inverse Lithography Techniques (ILT) with 193nm immersion lithography. In this paper, we investigate the manufacturing challenges of several Photonics devices using advanced ILT solutions and the SRAF insertion impact on delivering good litho quality including EPE, PVband and LER. We will demonstrate how our Calibre ILT solutions enable the manufacturing of the most challenging Photonics designs.

In our manufacturing process for the hard disk drive (HDD) recording heads, the home-brew pixelated-based inverse lithography is being employed in some critical lithography layers, providing significant improvement on pattern fidelity and process stability. Generally, the process-aware (defocus and dose) inverse lithography is realized through the stochastic gradient decent (SGD) method. In this paper, a widely used search algorithm Adam is introduced for our inverse lithography framework. The new algorithm utilizes the first and second moments of gradients to adapt the learning rate for each individual pixel during the stochastic searching process. Unlike SGD, such derived learning rate is invariant to the magnitude of gradient. In our experiment, we demonstrated reduced edge placement error (EPE), enlarged process window and tighter critical dimension (CD) distribution with Adam on our test cases of isolated features. We believe that the inverse lithography with Adam algorithm is also applicable to dense features with the similar benefits.

While technology is being developed, design rules undergo a number of revisions. An initial lithography model built with test patterns before the revisions inherently become inaccurate for the revised patterns. Preparing a new test layout and updating a lithography model every time design rules are revised is not practical, and cannot be a solution. We prepare some synthetic patterns in addition to initial test patterns. Synthetic patterns originate from popular test pattern generator (TPG), while projected design rule changes are taken into account. A challenge is to sort out the synthetic patterns which are really necessary in building a generic lithography model when they are used together with test patterns. Each pattern, either synthetic or test, is identified in image parameter set (IPS) space. For each test pattern in IPS space, two concentric spheres are drawn; outer one indicating the region where revised versions of test pattern may exist, and inner one indicating the region which is well covered by test pattern alone. Synthetic patterns that reside in the region bounded by the two spheres are kept, while the others are dropped. Clustering is now performed on test patterns and synthetic patterns separately, and representative pattern is drawn from each cluster. When a set of representative patterns are used to build a lithography model in 10nm memory devices, it achieves 43.5% lower CD root mean square error (RMSE) for revised design layout compared with only using a set of initial test patterns.

In this paper, we will present a machine learning solution targeted for memory customers including both assist feature and main feature mask synthesis. In a previous paper, we demonstrated machine learning ILT solutions for the creation of assist features using a neural network. In this paper, we extend the solution to include main features masks, which we can create using machine learning models which take into account the full ILT corrected masks during training. In practice, while the correction of main features is often visually more intuitive, there are underlying edge to edge and polygon to polygon interactions that are not easily captured by local influence edge perturbations found in typical OPC solvers but can be captured by ILT and machine learning solutions trained on ILT masks.

In making sensors require multiple processing by using different masks to accomplish, it needs reload and multiple aligning for a wafer in order to make a functional wafer, thus, the consuming for making mask are wasted, and used lamps toxic. In the study, a ULVLED stepper with Programmable LCoS or DLP as mask for multiple process wafer is proposed. By a programmable ultraviolet light-emitting diode (UVLED) array with a collimated lens as a transfer lens forms uniform source, to expose programmable LCoS or DLP as mask by using a 1 to 1 lithographic lens. Sensors and optical binary lens are easily made.

With the continuous improvement of chip integration level, resolution enhancement techniques (RET) has become one of the important technologies to promote the continued development of process nodes, such as source mask optimization (SMO), optical proximity correction (OPC) and sub-resolution assist feature (SRAF). Model-based SRAFs are generated by the guidance of the Continuous Transmission Mask (CTM) or SRAF Guidance Map (SGM). During operation, a threshold combined with the ridge is used to extract a suitable location for SRAFs. However, this generation method ignores many details, resulting in the need to constantly adjust SRAFs referring to the SGM/CTM in the subsequent optimization process, which will undoubtedly increase the simulation time. Therefore, we propose a contour line based SRAFs generation method. The extreme value region and the gradient of CTM/SGM will be displayed intuitively, so that more precise positions can be obtained at the initial SRAFs extraction. The SRAFs will be extracted from the extreme value region, and have a distribution similar to the final result. The gradient of the contour line can also be referenced in the following steps to guide the SRAF cleanup. During cleanup process, the SRAFs at high altitude region will have higher priorities to ensure the image quality of main patterns. Another advantage of this method is that when extracting rules from the model-based method, different SRAF priorities can be set according to the contour line and be used in the rules, so as to improve the accuracy of rule-based SRAFs.

In recent years, semiconductor demands have been growing to support on-line activity. And the needs of productivity improvement amongst chipmaker is higher than ever. ArFi light source’s modules life shall be targeting to one year cycle, and light source’s availability is improving is subjected as push to the limit and demonstrating an improvement year over year. To improve wafer output efficiency more, we need to focus not only on module lifetime extension but focus on to lithocell availability improvement which enabled by the alignment with PM time slot of the other scanner’s sub modules or chipmaker’s production cycle requirement in multiple year scale. Given these facts, this paper discusses Availability Maximization software function as Availability Maximization which is supported by the lightsource’s module replacement cycle extension by introducing emerging technologies and maintenance time reduction and optimization to fit into lithocell PM slot. Therefore, it provides the highest tool availability to chipmaker HVM environment invented by Giagaphoton’s unique and comprehensive solution.

A newly designed ArF immersion lightsource, GT66A is required to provide yield improvement on highly complexed multiple-patterning lithography and additional productivity to the chip makers. The DUV lightsource prospective, EPE needed to be paid attention in order to reduce LER/ LWR, Line Narrowing Module (LNM) demonstrates E95% stability improvement providing further OVL/ CDU improvement. In order to improve tool availability, GT66A key modules including LNM provides up to 50% expected life extension. Therefore, GT66A enables to provide high in availability with improved optical property for EPE enhancement simultaneously.

Layout classification is an important task used in lithography simulation approaches, such as source optimization (SO), source-mask joint optimization (SMO) and so on. In order to balance the performance and time consumption of optimization, it is necessary to classify a large number of cut layouts with the same key patterns. This paper proposes a new kind of classification method for lithography layout patterns based on graph convolution network (GCN). GCN is an emerging machine learning approach that achieves impressive performance in processing graph signals with nonEuclidean topology structures. The proposed method first transforms the layout patterns into graph signals, where the sum of several adjacent layout pixels is associated with one graph vertex. Next, the adjacent graph vertices are connected by the graph edges, where the edge weights are determined by the correlations between the vertices. Therefore, the layout geometries can be represented by the function values on the graph vertices and the adjacency matrix. Subsequently, the GCN framework is established based on the graph Fourier transform, where the input is the graph signal of the layout, and the output is its classification label. The network parameters of GCN are trained in a supervised manner. The proposed method is compared to the simple convolutional neural network (CNN) with a few layers and VGG-16 network, respectively. Finally, the features of different methods are discussed in terms of classification accuracy and computational efficiency.

Optical proximity correction (OPC) is regarded as one of the most important computational lithography approaches to improve the imaging performance of sub-wavelength lithography process. Traditional OPC methods are computationally intensive to pre-warp the mask pattern based on inverse optimization models. This paper develops a new kind of pixelated OPC method based on an emerging machine learning technique namely graph convolutional network (GCN) to improve the computational efficiency. In the proposed method, the target layout is raster-scanned into pixelated image, and the GCN is used to predict its corresponding OPC solution pixel by pixel. For each layout pixel, we first sub-sample its surrounding geometrical features using an incremental concentric circle sampling method. Then, these sampling points are converted into graph signals. Then, the GCN model is established to process the pre-defined graph signals and predict the central pixel within the sampling region on the OPC pattern. After that, the GCN is moved to predict the OPC solution of the next layout pixel. The proposed OPC method is validated and discussed based on a set of simulations, and is compared with traditional OPC methods.

It is widely known that the spectral shapes of light sources, represented by FWHM or E95 conventionally, have great impacts on the optical lithography performances. On the other hand, modern optical lithography requires more precise control of Critical Dimension (CD). Of the many factors impact the CD, OPE and Process Window (PW) play important roles in optical lithography. The Gigaphoton’s Spectral Engineering (SE) technique introduced in its latest light sources, which can generate a variety of spectral shapes, such as, top-hat spectra, multi-peak spectra in addition to conventional broadband spectra, can have substantial contributions to both PW enhancements as well as OPE optimizations. In the last report, as an example, we have shown that the PW of CH/VIA will be improved by the introduction of SE technique. However, the PW improvement is realized mainly by expanding DOF at the cost of EL. As users are interested in CD Uniformity (CDU), not PW itself, and the CDU depends on both focus and dose accuracies, a question that is likely to arise is, will the CDU be improved by the SE? In this report, we are going to show that, by the introduction of SE, users can expect significant improvements of CDU for semi-isolated or isolated patterns, at trivial costs of CDU deteriorations for dense patterns. For the OPE, although it is widely known that spectral width can be used in OPE tunings, but it has rarely been used in FABs, as a tuning knob. We are going to show that the spectral width control with SE will greatly improve both qualities and chances of OPE tunings.

Overlay (OVL) metrology targets are typically distributed across the scribe lines of the grid on a semiconductor wafer. However, OVL target placement across peripheral scribe lines or intra-field scribe lines cannot always describe the OVL measurement of interest, especially when the OVL distribution is of high order. The OVL measurement of interest lies within the device, in the center of the field or the center of die. This work aims to emphasize the need for intra-field metrology simulations to quantify the impact of scribe line target usage in the presence of a high order intra-field OVL map. The analysis will cover the impact of scanner aberration, target location, sampling and model error on OVL results. To complete the picture, a wafer map will be simulated with high order OVL error distributions both outer-field and intra-field. We will present the tradeoff between high sampling, target location and accuracy.

Calibration pattern coverage is critical for achieving a high quality, computational lithographic model. An optimized calibration pattern set carries sufficient physics for tuning model parameters and controlling pattern redundancy as well as saving metrology costs. In addition, as advanced technology nodes require tighter full chip specifications and full contour prediction accuracy, pattern selection needs accommodate these and consider contour fidelity EP (Edge Placement) gauges beyond conventional test pattern sets and cutline gauge scopes. Here we demonstrate an innovative pattern selection workflow to support this industry trend. 1) It is capable of processing a massive candidate pattern set at the full chip level. 2) It considers physical signals from all of the candidate pattern contours. 3) It implements our unsupervised machine learning technology to process the massive amount of physical signals. 4) It offers our users flexibility for customization and tuning for different selection and layer needs. This new pattern selection solution, connected with ASML Brion’s MXP (Metrology of eXtreme Performance) contour fidelity gauges and superior, accurate Newron (deep learning) resist model, fulfills the advanced technology node demands for OPC modeling, thus offering full chip prediction power.

The power spectral density (PSD) is a powerful mathematical tool for characterizing roughness as a function of frequency (or length scale). It is widely used for characterizing surface roughness and edge roughness, and in the semiconductor industry it is used to understand line-edge roughness (LER) and linewidth roughness (LWR). In this tutorial, the definition, measurement, and use of the PSD will be described for LER/LWR characterization. Sources of errors (biases, both systematic and random) will be discussed as well as their mitigation. Finally, interpretation of the shape of the PSD and its meaning in the context of patterning will be briefly addressed.

The extraordinary success story that is Moore’s Law required many technological components to come together at the right times. This tutorial will tell this story through the lens of one of the key components: the patterning materials, in particular the photoresists. Every chip ever produced has used some form of microlithography, usually photolithography, which has historically been the gating technology for how quickly features sizes could be shrunk. Starting with cyclized rubber resists, the industry went on to use DNQ Novolak systems for a quarter century, before switching wavelengths from near-UV to 248 and 193 nm, then to 193 nm immersion. Every one of these switches required the invention of a new photoresist platform, new resin systems and even new imaging concepts, such as the use of chemically amplified resists beginning with 248 nm. For the materials scientist, Moore’s Law has historically been a race to the next wavelength. This sequence of more or less frantic developments is coming to an end as we near the physical limits of microlithography. With the introduction of EUV lithography, the finish line of this race is in sight: today’s EUV resists are still far from perfect, and this presentation will cover their issues and the paths forward, but there can be no doubt that with EUV, we have reached what appears to be the Final Wavelength. However, the need for better, faster, cheaper process options will not go away, and bottom up technologies such as DSA, selective or self-aligned patterning, and other processes with atomic level precision will need to continue to be developed. The future will see new non-CMOS device types and possibly even circuits which function according to the laws of relativistic quantum physics, all of which will require new materials and bring new challenges. While photolithography is entering its end game, the job of the material scientists is far from done. The presented manuscript is a slide deck, not a formal SPIE conference proceedings paper.