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Curvilinear masks are coming. With multi-beam mask writers in production, leading edge mask shops now are able to write curvilinear masks in the same mask write times as any Manhattan masks [1, 2]. As Samsung and Luminescent showed long ago [3], curvilinear mask shapes produce the best wafer process windows. For 193i masks, curvilinear SRAFs have been demonstrated in reasonable time even with the traditional variable-shaped beam (VSB) writers with good wafer results. [4]
It is widely anticipated [5] by the luminaries of the industry that curvilinear ILT shapes either are already or will be used at least for hotspots in some leading-edge layers before 2023 for both 193i and EUV masks. ILT solutions have previously focused on Manhattanizing the output to make it suitable for VSB writing, instead of using curvilinear or at least piecewise linear polygons to be specified for the desired mask shapes. With multi-beam mask writing being widely available for the leading-edge nodes, manufacturing curvilinear ILT shapes is now possible. But what about the rest of the mask making infrastructure?
This paper introduces the session on curvilinear masks by surveying the constraints and considerations around introducing curvilinear masks to mask manufacturing. The other papers of the session will address the data volume and computational complexity issues with contour geometry in polygon-based processing of data. We take note of pixel-based manipulation of data being constant in run-time performance regardless of shape, whereas manipulation of contour geometry scales in run time based on vertex or edge count. This paper also reiterates that curvilinear MRC can be significantly less complex [6]. Other aspects of the mask infrastructure including metrology, inspection and repair will be discussed.
The paper concludes with a brief discussion about curvilinear wafer targets, or curvilinear designs [7]. It suggests that allowing certain curvilinear targets can make designs more manufacturable and more resilient to manufacturing variation on the wafer, while decreasing power consumption, increasing clock speeds, and making designs smaller.
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