The rapid progress of VLSI processing technology has recently raised a new demand for production equipment which is capable of multiple processes sequentially in the multi-chamber system. Mutli-chamber concept seems to be the major trend in the efforts to achieve development and production of sub-micron devices.

For multichamber and in-situ processing of microelectronic materials, there are few hundred steps in a manufacturing line. The design of such processing systems require careful simulation, modeling, and planning. Our basic approach is the idea of an interactive software design environment for equipment, process, and manufacturing line modeling and simulation, which provides a way to integrate the manufacturing line and its simulator tightly.

The vacuum environment is increasingly being used in manufacturing operations, especially in the semiconductor industry. Shrinking linewidths and feature sizes dictate that cleanliness standards become continually more strict. Studies at the Center for Robotic Systems in Microelectronics (CRSM) indicate that a controlled vacuum enclosure can provide a superior clean environment. In addition, since many microelectronic fabrication steps are already carried out under vacuum, self-contained multichamber processing systems are being developed at a rapid pace. CRSM support of these systems includes the development of a research system, the Self-contained Automated Robotic Factory (SCARF), a vacuum-compatible robot, and investigations of particulate characterization in vacuum and inspection for multichamber systems. Successful development of complex and expensive multichamber systems is, to a great extent, dependent upon the discipline called vacuum mechatronics, which includes the design and development of vacuum-compatible computer-controlled mechanisms for manipulating, sensing and testing in a vacuum environment. Here the constituents of the vacuum mechatronics discipline are defined and reviewed in the context of the importance to self-contained in-vacuum manufacturing.

Due to the rapid oxidation of metal surfaces, in vacuo preparation of metal substrates is needed to provide suitable growth surfaces. Surface characterization of the metal substrates or the subsequent epitaxial metal growths must also be performed under ultrahigh vacuum conditions. Transfers of the metal samples from preparation to growth to characterization facilities must be in vacuo to protect the highly reactive surfaces. This work has been performed with an in vacuo transfer system integrating a two-stage load lock, a remote plasma enhanced chemical vapor deposition chamber, a substrate preparation facility, a metals molecular beam epitaxy chamber, and a surface analysis system. This integrated process facility will be described with particular attention to the effects of sample preparation on the subsequent metals growth. Processing with the integrated facility has resulted in the growth of epitaxial metal films, alloys, multilayers, and superlattices. Processing with only in situ wafer processing has resulted in only textured polycrystalline growths. The metals molecular beam epitaxy system of the integrated facility will be described with special emphasis on epitaxial growths of metal thin films, alloys, multilayers, and superlattices from the Cu-Ni system.

This paper describes the design and construction of a multichamber integrated dielectric processing system. We describe a methodology for managing the design process of complex integrated-processing systems which includes model building and computer aided design. The advantages of a flexible modular approach to integrated processing are discussed. The finished system has three processing and analysis modules networked by a central server with capabilities for (i) remote plasma enhanced chemical vapor deposition (PECVD) of dielectric films, (ii) downstream cleaning of semiconductor surfaces, and (iii) in-situ materials characterization by Auger electron spectroscopy (AES) and reverse view low energy electron diffraction (LEED). With this integrated processing system we have the capability of depositing and analyzing Si-based heterostructures which can be fabricated to include any combination of silicon oxide; silicon nitride; silicon oxynitride; and amorphous, microcrystalline, or polycrystalline silicon layers.

As with any concept in its early stages or realization, there are many ways of thinking about what we call "process integration" in semiconductor manufacturing. In its most simple form, we consider it to be the combining of two or more sequential processing steps, normally performed in separate systems, into a unified process flow within one fabrication tool.

This paper describes effects of spin-on-glass (SOG) planarization layer etchback process on reliability of submicron vias for multilevel metalization. Resistance values of double-level metal via chains containing 4,000-200,000 vias in the 0.8-2.0 um size range have been measured. Mass spectra for outgas from SOG films have been studied in more detail. The SOG etchback process and the subsequent P-SiO layer deposition process have been executed in a multichamber CVD system. The multichamber processing can reduce the emission of outgas which degrades via yield and reliability.

A new integrated in situ approach to deposition and planarization of dielectrics is presented. This process uses a multi chamber deposition and etch system. Using plasma enhanced deposition a sacrificial layer or boron oxide is deposited over the dielectric material. Boron oxide is observed to flow as deposited resulting in a planarized surface. After deposition the wafer is transferred under vacuum to the etch chamber where the boron oxide is removed with a 1:1 dielectric to boron oxide etch. This results in a planarized dielectric surface. Effective planarization of 25 micron wide spacings can be achieved using this process.

This paper presents a manufacturable process to deposit dielectric films capable of void-free filling of submicron spaces between adjacent interconnect lines as well as local planarization of topography using conformal TEOS-based oxides and in-situ etch processes. The deposition planarization process is user programmable and is accomplished entirely in a single multi-chamber system (Applied Materials Precision 5000) in one cassette-to-cassette operation. Data on the step coverage and topographic gap filling characteristics of the TEOS oxide deposition and etchback sequences are presented. Analyses of material properties and the electrical stability of the TEOS-based oxide films deposited in this system indicate that the films are suitable for interlevel dielectric applications in submicron devices. Film properties such as stress, thermal shrinkage, density, moisture absorption, and dopant incorporation were characterized for the two types of low temperature TEOS-based oxides used in the process, and these are compared to the properties of low temperature SiH4-based LPCVD oxides. The results show that the TEOS films compare favorably to the "industry standard" SiH4-based films. SIMS analysis was used to investigate the purity of the TEOS oxides. The signals of aluminum, iron, and other trace metals were at or below their detection limits, for both the PE-TEOS and the thermal ozone-TEOS oxides. The carbon content of the PE-TEOS film was 0.8 atomic percent while both the thermal ozone-TEOS and the LPCVD SiH4 oxides had less than 0.2 atomic percent. Electrical stability of the composite TEOS oxides was evaluated using bias-temperature stress C-V analysis. Undoped and phosphorus-doped PE-TEOS oxides produced lower Hatband voltage changes than the reference LPCVD SiH4 oxides. The undoped PE-TEOS films were found to have mobile ion charge densities of 7.7*109 cm-2, compared with the LPCVD SiH4 oxide values of 1.2*1011 cm -2. Device level electrical testing of devices built using the TEOS oxides showed no electrical anomalies such as gate charging and the devices have successfully undergone reliability and lifetime testing.

Multichamber and in-situ technology are used to meet the challenge of manufacturing 16-Mb cost/per-formance DRAMs. The 16-Mb fabrication process is more complex than earlier 1-Mb and 4-Mb chips. Clustering of sequential process steps effectively compensates for both manufacturing complexity and foreign-material (FM) related defect densities. The development time of clusters combining new processes and equipment in multiple automated steps is nearly as long as the product development cycle. This necessitates codevelopment of manufacturing process clusters with technology integration while addressing the factors influencing FM defect generation, processing turnaround time (TAT), manufacturing costs, yield and array cell and support device designs. The advantages of multichamber and in situ processing have resulted in their application throughout the entire 16-Mb DRAM process as appropriate equipment becomes available.

Each generation of VLSI semiconductor technology is more complex than the previous generation. Therefore, to help minimize manufacturing costs, turnaround time and defect levels, process clustering has become an attractive alternative to traditional, nonclustering processing. A unique application to cluster processing is in-situ cluster processing, defined as multiprocess steps using various chambers under vacuum inside a single machine. The use of four single wafer reactors (SWR) combined with a common load-lock capable of deposition and etch processes was examined for spacer processes. Two examples will be discussed in some detail: spacer formation and recess/collar formation.

Finely focused ion and electron beams have been applied to processes of etching, implantation, and monitoring in multichamber in-situ processing systems. Each application has been evaluated and some remarkable achievements are reported.

We have investigated in situ cleaning of GaAs substrates with a HCl gas and hydrogen mixture prior to molecular beam epitaxy in a multichamber system. The chemical reaction during etching was monitored in situ and simultaneously using a quadrupole mass spectrometer. After etching, the reflection high energy electron diffraction patterns with reconstructed structures, such as (2x4) As-stabilized surface and (4x2) Ga-stabilized surface, were observed in the gas etched substrate surface. These structures suggest that the gas etched substrate surface is atomically flat, resembling an epitaxial layer surface. To study the effect of gas etching, the carrier depletion layer and the residual carbon impurity around the substrate epitaxial interface were measured by capacitance-voltage carrier profiling and secondary ion mass spectroscopy. After gas etching, the carrier depletion was greatly reduced, from 1.2 x 1012 to 1 x 101° cm-2. The carbon impurity around the interface also decreased by one order of magnitude. We then applied this etching technique to in situ cleaning of semi-insulating GaAs substrates prior to the growth of selectively doped GaAs/N-AlGaAs heterostructures having very thin GaAs buffer layers.

The flexibility of the remote plasma process qualifies it as a tool for multiple step processing. Cross-contamination of remote plasma processes via interactions of reactant gasses with the chamber wall deposits has been observed when hydrogen has been introduced as a downstream reagent gas. This has been observed for both substrate cleaning prior to epitaxy and during epitaxy. With proper precautions and chamber wall conditioning, the contamination problem can he eliminated. Thus, integration of multiple remote plasma processing steps into a single chamber is possible.

We have developed a new fine-beam assisted GaAs maskless etching system capable of nanofabrication; a focused ion beam (FIB) and electron beam (EB) combined etching system with a reactive gas nozzle. In this FIB/EB combined system, EB excited GaAs etching was successfully performed by irradiating Cl2 gas on a temperature-controlled substrate. 5KeV EB was raster-scanned in a 100pm X 20pm rectangular pattern on a GaAs surface. With special care to remove the native oxide layer, spatially selective etching was also confirmed on a cleaned GaAs surface by controlling the Cl2 pressure.

This paper describes the formation of heterostructure devices using multichamber, integrated-processing thin-film deposition systems with UHV-compatible inter-chamber transfer. We describe the application of remote plasma-enhanced chemical-vapor deposition (Remote PECVD) for deposition of semiconducting and dielectric thin films in representative device structures. Special attention is directed to: i) deposition conditions necessary for control of thin-film and interface chemistry; and ii) post-deposition-annealing for the stabilization of physical and electronic properties of the heterostructures, including the interfaces between the constituent layers.

The logical architecture of an expert system AEMPES (Advanced Electronic Materials Processing Expert System) for in-situ diagnostics and process monitoring of advanced electronic materials processing is described. It is a distributed AI system with both the end-process and in-process diagnostics and monitoring capabilities. Techniques of sensor fusion, spatial reasoning, machine learning, reasoning with uncertainty and model-based reasoning are employed in the system.

An in-situ spectroscopic ellipsometer system was used to monitor damage and film formation occurring on the surface of silicon wafers during 1200 eV argon ion etching. Ellipsometric data were taken on two kinds of samples, one kind had only a native oxide and the other had a thermally grown oxide. Interpretation of ellipsometric spectra was carried out using derived optical models. The models reflect the state of the sample and allow quantification of the damage kinetics occurring at the substrate surface. Results from these experiments illustrate not only substrate damage formation, but also surface interface changes.

A new spectroscopic phase modulated ellipsometer (SPME) is presented. As compared to other ellipsometric techniques like rotating analyzer ellipsometry (RAE), the phase modulation uses a high frequency modulation (50 kHz) provided by a photoelastic modulator. Then SPME allows at least two orders of magnitude faster real-time mesurements than RAE. Thus, SPME is particularly suitable for in situ real-time applications. New insights on phase modulated ellipsometry are given. In particular, it is shown that an optical model, taking into account the presence of higher harmonics in the modulation, leads to an improvement of the precision measurement. Therefore, it can be inferred that both RAE and SPME provide comparable high precision measurements. Moreover SPME can be combined with numerical data processing systems. A new Fourier analysis of the signal, based on the use of a high precision analog digital converter and a fast digital processor, is presented. The adaptation of the SPME to a deposition chamber is illustrated. In particular, the use of optical fibers in both optical arms allows an increase of the compactness of the ellipsometer. Four detectors can be used simultaneously providing the spectroscopic capability for real-time applications. On-line connexions between the data acquisition system and external analog signals and triggers can also be used. Thus phase modulated ellipsometry appears a powerful technique for in situ control processing applications.

Optical emission spectroscopy has been established as a powerful and versatile method for in-situ diagnostics in ion beam etching. In broad argon and oxygen beams particle energies could be determined by the detection of Doppler shifted emission lines. The line widths correspond to the beam divergence. The Doppler resolved emission spectra also provide information on collision phenomena. Moreover etch products could be detected during ion beam etching of silicon, silicondioxide, and an organic photoresist. A new method is introduced for in-situ etch rate determination and endpoint detection applicable to reactive ion beam etching and reactive ion etching as well. Interference of light reflected at the surfaces of a thin layer and at the underlying substrate is used for this purpose. In contrast to the conventional interferometric procedures no additional light source is required. The plasma or beam itself serves as a light source. As an advantage compared to He-Ne laser interferometry, the method presented here offers the opportunity of better resolved determination of the film thickness variation because shorter wavelengths are available in general. A sharp endpoint signal is, additionally, obtained in many cases if emission lines of an etch product or an etchant (loading effect) are used.