This PDF file contains the front matter associated with SPIE Proceedings Volume 12054, including the Title Page, Copyright information, Table of Contents, and Conference Committee listings.

Direct self-assembly (DSA) can form periodic fine patterns by the repulsive forces between different polymers. As one of the candidates for next-generation lithography, it has been evaluated for semiconductor manufacturing processes for the past 10 years1-11 . Reports of DSA processes using Chemo-epitaxy show many line-and-patterns formed using lamellas and few hole patterns using cylinders. The reason why it is difficult to form a hole pattern is that the direction of line-and-space misalignment is one-dimensional, whereas in the case of a hole, it is two-dimensional, so dislocation defects are likely to occur and process control is difficult. On the other hand, the pitch of hole patterns in semiconductor devices is shrinking year by year, and in the future it may not be possible to form them all at once even with EUV (Extreme ultraviolet) lithography. Therefore, it is expected that there will be an increasing demand for shrinking patterns using DSA additionally. In this presentation, we report on the method of forming a hole pattern by the chemo-epitaxy process and the process condition setting, and discuss the possibility of application to the semiconductor process.

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. In this review paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. In addition, we describe recent efforts to develop pattern transfer processes that can be used to address edge placement error. As a final topic, we describe Canon’s efforts in developing a sustainable future and touch on how new methods can be applied to reduce waste and enable environmentally friendly solutions.

NanoImprint Lithography (NIL) is not a novel technology anymore1 but huge progress has been achieved for its industrial introduction since its first reporting. One of the main evolutions concerns the use soft stamp media2 ,which is now a standard technology. EVG introduced this technology with a full wafer imprint solution (the size of the stamp corresponds to the size of the wafer to print)3 and results obtained since five years are at the state of the art. Repeatability, uniformity, sub-50nm resolution and high aspect ratio patterns are addressed at the same time4–6 . Nevertheless, some challenges still remain, as e.g overlay7 and in particular the distortion phenomenona 8 , which contribute to the remaining overlay next to global translation and rotation. This study is focused on distortion effect which appears during NIL process using flexible backplanes and its minimization by using different materials. A polymer backplane is compared with a glass backplane which are used as carrier to the soft stamp material. A dedicated methodology to precisely measure this distortion is implemented to remove global alignment signature. Distortion signature is firstly evaluated with a standard soft stamp material and process of reference already established. Distortion fingerprint mapping is obtained for each wafer. Thanks to this mapping, a monitoring distortion plot is extracted, in order to follow the evolution of the distortion depending on wafers (wafer-to-wafer) and lots (lot-tolot). This study highlights that the use of a glass backplane developed by EVG clearly allows to improve the distortion in terms of magnitude but also of stability.

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. DRAM memory is challenging, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL an attractive solution. The purpose of this paper is to review the performance improvements related to edge placement error (EPE) for NIL. Key EPE components include overlay, local critical dimension uniformity (LCDU) and global critical dimension uniformity (GCDU). In this work, we review each component, summarize current capability and present a roadmap for improving EPE to meet future generations of DRAM devices.

Scaling the cell size of phase change memory (PCM) is crucial for reducing reset current and enabling energy-efficient switching. Because memory arrays have a regular pattern, block copolymer directed self-assembly (DSA) is uniquely suited for reducing patterning costs for future nanoscale PCM. Here, we realize the fabrication and electrical characterization of a PCM array with Ge₂Sb₂Te₅ phase change material featuring 20-nm cells patterned by DSA. Our confined cell PCM devices with ~20 nm bottom contact diameter switch at ~150-200 μA, while maintaining a resistance on/off ratio of ~10. We also discuss some factors for further consideration for improving the limited endurance of such nanoscale confined cell PCM. Our demonstration would inspire further reduction of the PCM cell size below 10 nm using high-χ block copolymers, thus paving the pathway towards ultrahigh density memory.

The application of curvilinear masks for DUV lithography has demonstrated benefits over Manhattan masks for improved process window, mask consistency, sidelobe printing control and MRC. However, the prior high cost of using curvilinear masks has limited the usage to critical areas and prevented its broader adoption in production. With recent technology advancements, multi-beam mask writers are capable of meeting specifications of advanced patterning nodes, and curvilinear masks can now be extended to advanced EUV lithography generations. ILT is known for its advantage of creating a patterning-optimized curvilinear mask through field operations. It has been used to solve the most challenging lithography problems with superior quality. Computational costs have previously limited widespread ILT deployment to only the most advanced production mask synthesis flows. To create curvilinear masks for full-chip layout, a faster curvilinear OPC solution for less critical regions will be a valuable complimentary option to curvilinear ILT. In this paper, we will present a hybrid curvilinear mask solution with ILT and Curve OPC for full-chip EUV layers. Results of full-chip EUV in lithographic performance and runtime will be compared among different solutionsincluding traditional Manhattan OPC, Curvilinear ILT and hybrid machine learning (ML) ILT plus Curve OPC. Another important factor of curvilinear mask advancement is data volume. We will present our Curve OPC solution with Cubic Bezier curve to control the data volume of curvilinear masks. The mask write process is playing an increasingly important role in overall manufacturing flow. Therefore, we also present an extended mask synthesis flow utilizing a mask error correction (MEC) solution for curvilinear masks written by a multi-beam writer.

MBM-2000, the latest multi-beam mask writer of Nuflare Technology, Inc. (NFT), have achieved reasonable writing time in mask fabrication of 3nm semiconductor technology node, which demand small curvilinear patterns in EUV masks and curvilinear OPC patterns in optical masks. For less line edge roughness and better pattern fidelity, however, the demand of lower dose sensitivity resists keeps increasing. In such a situation, the beam exposure time can be the main bottleneck of the writing time. In order to meet the demand, NFT has developed MBM-2000PLUS, which achieved high beam current density of beamlets ×1.3 larger than MBM-2000. As the result, the writing time became constant up to 170 μC/cm² exposure dose condition without confinement by beam exposure time. Even at the region of exposure dose confinement, the writing time became 20% less than MBM-2000 at 200 μC/cm² dose condition. In addition, charge effect reduction (CER), which is an electron optics system reducing resist charge effect, has been upgraded from MBM-2000 for improving image placement accuracy. Furthermore, MBM-2000PLUS inherits pixel level dose correction (PLDC) function from MBM-2000 as the solution for less edge placement error and better pattern fidelity. In this paper, those features of MBM2000PLUS are highlighted including improvement of pattern fidelity by PLDC function. In order to verify PLDC, a new methodology of quantitative evaluation of pattern fidelity using sine-shape pattern is introduced.

Helical structures with novel optical and mechanical properties have been demonstrated and are commonly used in different fields such as metamaterials, microfluidics and cell scaffold. None of conventional fabrication methods has the throughput or flexibility required for patterning large surface area with tunable pitch. In this paper, we report a novel method for high-throughput volumetric fabricating helical structures with tunable shape based on multiphoton polymerization (MPP) using single-exposure, self-accelerating beam with adjustable rotating intensity profile. The lightfields are generated based on high-order Bessel modes and an analytical model is derived to describe the generation and propagation of light-fields. The method is used to fabricated micro-helices with different pitches and handedness in SU-8 photoresist. Beam splitting and galvo-scanning can be implemented in the system. The fabrication of large-scale helical matrices is demonstrated. Compared to point-by-point scanning, our method increases the fabrication throughput by orders of magnitude, paving the way for adopting MPP for mass production of functional devices in many industrial applications.

The feature dimensions of integrated circuits are becoming smaller and the fabrication, metrology and inspection is becoming harder to be fulfilled. Fast-writing of long respectively large nano-features with Scanning-ProbeLithography and their inspection with an Atomic Force Microscope (AFM) is a challenge, for the accomplishment of which the Nanofabrication Machine (NFM-100) can serve as a beneficial experimental platform for basic research in the field of scale-spanning nanomeasuring and nanofabrication. The NFM-100 has an integrated tipbased system, which can be used as an AFM as well as for Field-Emission Scanning Probe Lithography (FESPL). The combination of both systems offers the possibility to fabricate and analyze micro- and nanostructures with high resolution and precision down to a single nanometre over a large area of 100 mm in diameter in a single configuration without tool or sensor change. Thus, in contrast to conventional optical inspection and alignment systems, the NFM-100 offers the potential for full lithographic and metrological automation. For FESPL, the implemented active probes enable an in-situ inspection capability, a quantitative mapping at unprecedented resolution, as well as an integrated overlay alignment system. In this paper, the basic set-up of the NFM-100 as well as the capability of the system for long range AFM scans and FESPL is demonstrated.

Improved performance and package form factors are shifting traditional designs toward higher density and 3D vertical integration concepts. The introduction of finer RDL lines/spacings provides higher performance but reduces the options for integration and electrification design rules at the package and substrate levels due to potential parasitic electrical effects. In this work, we evaluate high-performance chemically enhanced positive-tone photoresists tailored for high-resolution fine-pitch RDL and μ-bump/μ-pillar fabrication to achieve high aspect ratios and employ maskless exposure to demonstrate their patterning performance. Resolution testing, focus position, and exposure matrices, including resist sidewall profiles, are discussed with respect to 2/2μm line/space (L/S) requirements and beyond for heterogeneous integration designs.

Imaging capability of surface plasma based nano-patterning is discussed in this article. The imaging capabilityof 1:1imaging ratio is the basis, which is different with the interference lithography with the frequency multiplicationontheimage plan. In this article, “Superlens” is discussed. The imaging capability evaluation is based on the rigorouselectromagnetic modelling of Finite Element Method. Theoretical analysis and numerical evaluation are given, detailedimpact evaluation of a variety of important parameters to the imaging capability is presented.