This PDF file contains the front matter associated with SPIE Proceedings Volume 12496, including the Title Page, Copyright information, Table of Contents, and Conference Committee information.

In August 2022, President Joe Biden signed into law the CHIPS and Science Act. The CHIPS Act established a CHIPS for America Fund, totaling approximately $50 billion, for the U.S. Department of Commerce to administer to strengthen semiconductor manufacturing in America, where the integrated circuit was first invented. In addition to the construction of new fabs, CHIPS for America addresses the need for a resilient domestic microelectronics supply chain of materials and equipment suppliers, and a workforce trained for a range of technical capabilities. This talk will provide details about the rapidly developing CHIPS for America program, including the Research and Development Office, along with updates and some examples to illustrate the CHIPS vision for interaction with the semiconductor community.

High-NA EUV lithography represents the next chapter in advancing Moore’s Law. The relentless march toward progressively tighter geometries drives a reliance on pitch-division and multi-patterning techniques such as SADP, SAQP, SALELE, and others to overcome lithographic resolution limitations. Unfortunately, these approaches come with a cost in the form of extra lithography steps and increased process complexity. In technology nodes that are heavily dependent on pitch-division and multi-patterning, overlay control becomes extremely challenging, as tighter budgets are required to compensate for the additional sources of edge placement error and control of a current layer reticle to multiple underlayers is required. In recent years, the improved resolution of Low-NA EUV has helped to replace 193 nm immersion-based pitch division schemes with direct print, greatly reducing process complexity and thus providing a degree of respite for overlay control. However, as patterning requirements continue to tighten in accordance with Moore’s Law, even the Low-NA EUV becomes insufficient for direct patterning of the required geometries, forcing a return to pitch division. Intel intends to avoid Low-NA EUV + pitch division and move aggressively to High-NA EUV lithography for production in 2025. Unlike previous generation lithography platforms, High-NA EUV does create some additional challenges for overlay control and this talk will be focused on addressing those items.

Seeing an increasingly critical role of MI in the semiconductor industry, in this keynote, we will first review the evolution of the MI technologies in the last few decades, and then discuss the challenges we are presently engaging in, focusing on the EUV era metrology topics: thin resist, 3D and massive measurement. Most importantly, as an obligation of one of the leading equipment suppliers in this field, we will present a vision for the future technologies, in response to the keynotes from the device makers in recent years, mainly focus on electron beam tools but also to cover a certain range of different field technologies.

Scanning electron microscopy (SEM) is commonly used for line edge roughness (LER) measurement; however, it is difficult to achieve high-precision LER measurement of photoresists because exposure to an electron beam (EB) causes shrinkage of the materials. The differences in the 3D sidewall shape before and after shrinkage have not been investigated in detail. In this study, EB-induced photoresist shrinkage was observed by employing the atomic force microscopy with tip-tilting technique (tilting-AFM), which enables high-precision observation of the vertical sidewall of the pattern. In the experiment, the shrinkage deformation was observed by measuring the same photoresist pattern with the tilting-AFM before and after EB exposure (by SEM observation) on the pattern. The results show that the sidewall was smoothed by EB exposure. Further, the tendency of changes in LER (roughness parameters) was observed. This measurement technique can be used to better understand photoresist materials and to improve the LER measurement by SEM.

Shift happens due to electron beam tilt in scanning electron microscopy. To measure this aberration effect with submilliradian uncertainty, and to calibrate scale factor and correct scanfield distortion, we introduce conical frustum arrays as multifunctional reference structures. Our concept shows promise for new accuracy in scanning electron microscopy.

With the growing adoption of EUV lithography in both Logic and DRAM, the stochastics associated with EUV lithography has highlighted the need for accurate line roughness metrology. One of the approaches suggested to reduce stochastic effects is to transition to MOR (Metal Oxide Resist) from the traditional CAR resists. The CDSEM is the primary workhorse used today to measure line roughness in an inline environment. However, it is known that roughness reported by CD-SEM is dependent on the image acquisition conditions and the metrology algorithm settings. On the other hand, SEM metrology for EUV now requires low landing energies to minimize resist damage and increase contrast on thin high NA EUV resists ^[3]. However, this combination of low-dose scanning and low landing energies significantly lowers the contrast of the SEM image leading to higher reported roughness values using traditional roughness metrology algorithms. To understand and reduce the dependence of roughness on SEM image noise, we acquired images with different imaging conditions on a post-etch wafer and thin-resist EUV wafers with different stacks. The focus of this study is to demonstrate a novel roughness metrology algorithm that reduces the sensitivity of image SNR to roughness compared to traditional metrology methods. In this paper, we provide comprehensive guidelines for measuring unbiased roughness on thin EUV resist wafers in terms of roughness metrology and scanning conditions. We hope this work can provide the basis for understanding the roughness transfer from litho to etch and better characterize EUV lithography.

In this study, we applied the PointRend (Point-based Rendering) method to semiconductor defect segmentation. PointRend is an iterative segmentation algorithm inspired by image rendering in computer graphics, a new image segmentation method that can generate high-resolution segmentation masks. It can also be flexibly integrated into common instance segmentation meta-architecture such as Mask-RCNN and semantic meta-architecture such as FCN. We implemented a model, termed as SEMI-PointRend, to generate precise segmentation masks by applying the PointRend neural network module. In this paper, we focus on comparing the defect segmentation predictions of SEMI-PointRend and Mask-RCNN for various defect types (line-collapse, single bridge, thin bridge, multi bridge non-horizontal). We show that SEMI-PointRend outperforms Mask R-CNN by up to 18.8% in terms of segmentation mean average precision.

For the most advanced nodes, edge placement errors are typically dominated by stochastics, necessitating a rigorous stochastics approach to modeling and measuring edge placement errors and their contributors. In this work, a new approach to developing an edge placement error (EPE) model useful for lot dispositioning or EPE budgeting is presented. Approach: As an example of the proposed approach, a rigorous EPE model is developed for the case of complementary lithography, where dense lines and spaces are cut with a second patterning step. This model gives rise to the generation of an Overlay Process Window, the range of overlay errors that can be tolerated in the presence of stochastics critical dimension and placement errors of the individual layers. The resulting model uses only measurable quantities and allows the prediction of EPE-based failure rates for the purpose of lot dispositioning. One interesting outcome is that Angstrom-level changes in the 1-sigma stochastics terms produces nanometer-level changes in the overlay process window. This new EPE modeling approach provides a more rigorous and accurate method for lot dispositioning and EPE budgeting than prior approaches.

As EUV lithography transitions to high volume manufacturing, actinic photomask inspection tools at 13.5 nm wavelength are attractive for understanding the printability of EUV mask defects, as well as for in-fab monitoring for possible defects emerging from extended use. Ptychography is a lensless imaging technique that allows for phase-and-amplitude, aberration-free, high-resolution imaging in the EUV. Moreover, sources based on high harmonic generation (HHG) of ultrafast lasers are a proven viable coherent light source for CDI, with flux sufficient for rapid large-area inspection and small-area imaging. By combining CDI and HHG, we implemented actinic EUV photomask inspection on a low-cost tabletop-scale setup. Moreover, we propose and demonstrate a solution to the decade-long challenge of ptychographic imaging of periodic structures through careful illumination engineering.

Optical Critical Dimension (OCD) spectroscopy is a reliable, non-destructive, and high-throughput measurement technique for metrology and process control that is widely used in semiconductor fabrication facilities (fabs). Wafers are sampled sparsely in-line, and measured at about 10-20 predetermined locations, to extract geometrical parameters of interest. Traditionally, these parameters were deduced by solving Maxwell’s equations for the specific film stack geometry. Recently advanced machine learning (ML) models, or combinations of ML and geometric models, has become increasingly attractive due to the several advantages of this approach. Advanced node processes can benefit from more extensive data sampling, but this conflicts with measurement cycle time goals and overall metrology tool costs, which cause fabs to use sparse sampling schemes. In this paper, we introduce a novel methodology that allows wafers to be sampled sparsely but provides the parameters of interest as if they were densely measured. We show how such a methodology allows us to increase data output with no impact on overall measurement time, while maintaining high accuracy and robustness. Such a capability has potentially far-reaching implications for improved process control and faster yield learning in semiconductor process development.

For CMOS image sensors fabrication, deep trenches are commonly incorporated in the device to isolate the individual pixel one another within the pixel matrix. These etched structures typically exhibit a high aspect ratio of 1:20 and controlling such narrow and deep object is a challenge for inline metrology. In a manufacturing environment, the preferred method for trench height measurements remains the optical scatterometry (OCD) technique as being very sensitive and reliable. Still, it requires time and resources for model construction and validation. It appears then that an analysis of its predicted sensitivity could be a valuable pre-step before starting any activity on large periodical objects where OCD sensitivity can reach its limits. In this study, we tested this approach for deep trench structures with CD dimension in the range of 100nm to 1400nm and the depth from 100 nm to 5 μm. The periodicity (pitch) was fixed at CD*2. At first, 3D Mueller scatterometry signatures were modelled selecting spectroscopic ellipsometry acquisition configurations according to industrial most common ones. Thanks to an optimized RCWA (Rigorous Coupled Wave Analysis) code developed inhouse, calculation durations were reduced enough to allow massive data generation. By implementing a sensitivity analysis approach that uses Sobol coefficients, the sensitivity of the OCD metrology technique is here evaluated for each CD and depth values. More particulary, it will be illustrated by a CD range of ±10% of 350nm and with the depth of the trench varying from 100nm up to 5μm. As a results, a sensitivity frontier can be estimated at around 3μm, a critical depth value above which OCD in the given configuration is no more sensitive to the metrics determination. Such observation will be further discussed by analysis of convergence evaluation.

A comprehensive picture of the stress evolution within arrays of through-silicon-vias (TSV) is developed using in-line Raman spectroscopy. A set of wafers with different TSV geometries and metal seed liner thicknesses is exposed to various annealing conditions. Monitoring the Si-Si phonon mode shift between the vias, the influence of via geometries and processing conditions on the stress in the Si substrate is characterized non-destructively. Compressive stress is found in close proximity to the TSVs post Cu fill, as expected. However, for arrays with small TSV pitches, the substrate does not fully relax in the space between the vias, but rather tensile stress accumulates within the arrays. This inter-via stress increases with decreasing TSV pitch, accumulates towards the center of the arrays, and strongly depends on the annealing conditions. High resolution Raman maps within the arrays reveal the full picture of stress distribution in the TSV arrays. By using different excitation wavelengths, the variation of the stress with depth in the Si wafer is probed. The findings demonstrate the value of in-line access to process-dependent stress information. This knowledge helps to define design ground rules for highest device performance or to maximize the useable area on the wafer for logic devices.

A neural network-assisted spectral scatterometry method is presented to measure multi-dimensional critical dimensions (CDs) on high aspect ratio (HAR) structures with micron or submicron scales. With the rise of 3D integrated circuit packaging, there is a need for accurate characterization of HAR sub-micron structures. This method uses DUV scatterometry and a broadband light source from DUV to visible light to gather multi-channel reflection data. The inverse modeling method and artificial neural network model enable accurate measurement of multiple CDs of test structures. The results showed accurate measurement of deep trench critical dimensions with a nominal line width of 0.6 μm and aspect ratio up to 5:1, with accuracy within a few nanometers comparable to SEM results using the same sample.

The adoption of tier stacking (dual deck) leads to increasingly high aspect ratios and poses challenges in controlling overlay, tilt, and misalignment in the manufacturing processes for next generation 3D NAND devices. In this work we address metrology challenges such as tilt and overlay separation, measurement robustness influenced by process variation, and nonlinearity of spectral response to asymmetries. We show that Mueller measurement can separate overlay and tilt signals through distinct spectral response analyzed by a machine learning method with reference data. To reduce asymmetry measurement errors caused by process variation such as critical dimension (CD) and thickness changes, we propose and demonstrate improvement of tilt measurements on blind test wafers by feeding forward CD measurement results to the analysis of tilt signal. We also investigate nonlinear regression and show its capability to extend overlay measurement limit from linear response range, ±0.25pitch, to ±0.43pitch. In addition, for small structural asymmetries introduced by channel hole tilt, test RMSE is reduced by 20–40% from nonlinear regression alone or combined with CD feed-forward. We demonstrate that spectroscopic Mueller matrix measurements, paired with advanced machine learning analysis, provide nondestructive and accurate measurement of tilt, overlay, and misalignment for 3D NAND devices with high throughput and fast recipe creation.

A novel wafer edge quality inspection method based on analyzing curved-edge diffraction patterns is introduced in this paper. The diffraction patters, being collected through two approaches: (1) single point scanning method and (2) areal imaging method, are affected by edge topography, edge geometry and defects. After applying statistical feature extraction methods and wavelet transform to the collected fringe data, corresponding features of various defect modes were further extracted. In summary, both proposed methods enabled characterization and identification of various wafer edge defect modes and shed light on automatically wafer edge defects detection and categorization.

During metrology overlay recipe setup typically a wide range of different target designs are present to select from. The main goal of recipe setup is to select the most accurate target type-recipe combination at ADI (after develop inspection) without additional external information that can be used for production on a large set of wafers. We will introduce a method based on blind source separation to disentangle the contributions of target asymmetry and the overlay of the targets. Based on this separation, the most accurate target-recipe combination can be selected. On top of selecting the most accurate target-recipe combination, it is important to stabilize the difference between the overlay on device and the overlay as measured on the target. In order to increase that stability we will introduce advanced algorithms in the ADI measurements that use measured asymmetry parameters to correct for inline target asymmetry variation. We will show a metrology to device matching improvement of up to 40% on product wafers.

In this paper we have evaluated alignment and overlay for a Ruthenium Direct Metal Etch process. Depending on the integration strategy, line resistance and lithography requirements, a process with no remaining topography may be preferred from a lithography point of view, but due to the Ruthenium light absorption alignment and overlay through a thick Ruthenium layer will be challenging. In this paper we have studied the maximum thickness of Ruthenium for which the alignment sensor can still detect the alignment marks below and quantify the quality of diffraction-based overlay on an ASML YieldStar overlay metrology tool.

The on-device and target-less overlay (OVL) measurement adds various challenges to the conventional target-based one.¹ Most of the common solutions are based on the use of high voltage SEM to have a high resolution and see-through capabilities to see both layers entirely. To ensure repeatability and robustness the measurement is also generally realized on dedicated targets.^2–4 Another approach is explored in this work : it consists of a direct measurement on the device itself, without any dedicated target and using a CD-SEM that do not have see-through capabilities. To avoid any damage on the final device and to ensure a partial vision of the bottom layer, the measurement is realized post etch. What can a true on-device, target-less, SEM overlay metrology reveal of the process? To answer this question, a custom design-based on-device CD-SEM overlay metrology was developed.⁵ It allows measuring the overlay on any bilayer 2D structure, even partially hidden, provided that sufficient edges are visible. Thanks to this post-processing capacity to measure on partially hidden patterns, the CD-SEMs from the current tool park can be used and non-transparent layers can be investigated. After demonstrating the capability of the previously mentioned solution on synthetic SEM images,⁶ by taking advantage of the versatility of the method and of an improved bilayer contour extraction algorithm, one product wafer was measured densely at different steps of the process on several patterns. These extensive measurements aim to reveal overlay signatures at different spatial frequencies: intra-field, intra-chip and even inside a random logic array. This paper details and interprets the observed overlay measurement with models while investigating the matching between the different measurement patterns and the mismatches with the optical overlay. To conclude, the contour-based metrology offers the capability to extract highly valuable information from CD-SEM images and represents a great opportunity for on-device overlay measurement. By measuring directly the products’ patterns, the developed metrology shows a mismatch between optical and SEM measurements up to a couple of nanometers. A hybrid model, mixing SEM and optical measurements reduced by 15% the on-product residuals. Additionally, the local overlay variability could be evaluated and low amplitude chip signatures have been observed. This new information will help process engineers to improve the process characterization, leading to a better process control that results in an improved reliability.

The advanced logic node is continuously shrinking toward sub-nm node and EUV lithography is the one of main drivers to reach better patterning resolution resulting in reduced process steps. Along with this design rule shrink, On Product Overlay (OPO) requirement has been critical to the device yield making the accuracy and stability of optical overlay measurement to become primary concern on the lithography process control. Historically Optical Microscope (OM) ADI overlay was accepted and the standard for control to meet OPO requirements. Along the past years, as OPO budget diminishes with node-to-node, OM overlay required additional supporting reference data to compensate the inherent accuracy problem. Industry adopted the accuracy correction knob with High Voltage SEM (HV-SEM) at post etch, also known as SEM AEI overlay. The SEM AEI overlay measures the error contribution of different process influence and the overlay mark to real device pattern overly bias together. The inaccuracy of OM ADI overlay has been treated as a non-correctable error components till the on-device overlay measurement of HV-SEM after etching was enabled to compensate the delta known as Non-Zero Offset (NZO) or Mis-Reading Correction (MRC). Today the HV-SEM on-device overlay measurement at AEI is widely adopted as one of critical component to meet the OPO requirement enabling scaling for all types of advanced CMOS devices production. The main driver of On-Device-Overlay (ODO) measurement at AEI step is the see-through imaging capability to see all relevant layers through the stack even though the measurement step/time differs on the same wafer of the ADI optical overlay measurement are ranging from few to two-digit days depending on the process complexity. There has been an increasing need for a faster response of overlay measurements to close the overlay control loop and breakdown the device to target error versus the process overly induce component – in other words, to correct in the right step. This leads to the necessity of SEM ADI overlay measurement. With the recent e-Beam evolution of more higher landing energy, probe current and improved Total Measurement Uncertainty (TMU) performance, SEM ADI overlay measurement is enabled and considered to show the performances to meet market requirements on the selected layers of interest. In this paper, we would like to demonstrate the enablement of SEM ADI overlay measurement including the accuracy comparison with OM ADI overlay on the DBO scribe target versus real device pattern measurement performance. With SEM ADI and AEI overlay measurement on the same patterns, we could also demonstrate the error breakdown between optical target to device and from ADI to AEI process induced error which will enable the better correctable methodology to minimize NZO/MRC. In addition, this process contribution to error breakdown could be extended to improve, in the future, the Edge Placement Error (EPE) control.

In recent years, the overlay specifications of advanced semiconductor devices have become extremely stringent. This challenging situation becomes severe for every new generation of the device development. However, conventional overlay metrology systems have limited throughput due to their point-based nature. Here, we first demonstrate the novel imaging Mueller-matrix spectroscopic ellipsometry (MMSE) technique, which can measure the overlay error of all cell blocks on a device wafer with extremely high throughput, much faster than conventional point-based spectroscopic ellipsometry (SE) technologies. It provides the super large field of view (FOV) ~ 20 × 20 mm² together with high sensitivity based on Mueller information, which will be truly innovated solution not only for the overlay metrology, but also for critical dimension (CD) measurement, eventually maximizing process control and productivity of advanced node.

Tool-induced shift (TIS) is a common method used to quantify measurement error or accuracy of an overlay (OVL) metrology tool and is often attributed to tool asymmetry issues. In a previous paper, we introduced Modeled-TIS (mTIS), a machine learning (ML) based algorithm to predict per-site TIS correction on Image- Based Overlay (IBO) measurements. Recently, we adapted mTIS to support the requirements of high-volume manufacturing (HVM) in 3D NAND production. During our work in an HVM environment, we observed that the mTIS model is sensitive to complex process variations and many tool states. Such variations can change the measurement distribution and deteriorate the mTIS accuracy and reliability over time. In this paper, we present an automatic retrain triggering mechanism (“Trigger”) to monitor and adaptively update mTIS. The proposed methodology incorporates statistical and unsupervised ML algorithms which automatically detect shifts in measurement distribution, and initiate data collection to continuously adjust the model to process variations and tool states. The proposed mechanism does not require periodic retraining but rather initiates data collection and model updates only when required. Trigger chooses the wafers which possess novel information reducing the number of wafers required for the training and time to the model, critical requirements for our customers. We demonstrate the mTIS results of Trigger on various 3D NAND layers running in production. Finally, our approach can also be applied to future ML-based solutions.

In this paper the use of the EPE metric directly in the process optimization method for a DRAM use case has been researched. We show that EPE-aware optimization, using scanner dose and overlay control sub-recipes, is outperforming conventional optimization in terms of EPE Dies in Spec. Hence, it can be expected that also device yield can be improved by EPE-aware control.

As the term EPE was coined in the 1990ties, more recently a more inclusive definition of EPE has been proposed. Meanwhile semiconductor manufacturers see EPE as one of the main performance metrics enabling further shrink. In this paper we will give an update on the latest developments on EPE. Considering logic and memory use cases we will present evaluations of the EPE budget, including OPC model accuracy, overlay, CDU fingerprints for intra-field and inter field, overlay and local CD and placement error. The EPE fingerprint characterization is used to optimize scanner control for EPE performance on product. We will show how we can optimize the measured EPE fingerprints using scanner actuators.

Variability control has been a key enabler for achieving continuing technology shrinks in both logic as well as DRAM. With ever-tightening requirements, simple one-dimensional metrology and control aspects, i.e. separate variability control for CD and overlay, are no longer adequate [1]. To improve on this approach, simultaneous control of more than one parameter has been discussed to minimize the parametric yield impact. One such example is to improve edge placement error (EPE), a metric where overlay and CD metrology are combined [1]. In this work, we will revisit the EPE concept from the perspective of using established methodologies used in yield modeling. Rather than starting with a litho-centric approach, we cast the problem as a parametric yield loss mechanism driven by patterning parameters. In contrast to the widely disseminated EPE budget that originates from a patterning process-centric view, we introduce a modified analysis framework. The development of the approach discussed in this work starts with well-known yield engineering approaches rooted in defectivity modeling/statistics. It then proceeds towards quantifying and thus allowing a statistically sound quantification and thus prioritization of patterning (i.e. litho or post etch) improvements based on their impact on the yield loss Pareto. In doing so, the new formalism sheds light on what aspects of the EPE distribution most prominently affects yield loss. It also reveals that the ratio of potentially failing instances with a die and the max number of fails tolerable before the die fails plays a role in formulating any kind of budget approach. When putting our concepts to the test we discovered that there is yet another significant contributor affecting the acceptable variation range. We find that the “rigid structure approach”, an inherent assumption in any budget breakdown, and feature-to-feature interactions drive a significant reduction of the available processing tolerances. We attribute this mechanism to the 3D aspects of the patterning process and present a model that can handle the interactions. Finally, we discuss our approach to addressing the fact that process variability happens on length scales that cover several orders of magnitude. We developed a physical budget breakdown that attempts to optimize the tradeoff between sample size and the ability to capture variability over this wide range of length scales. We will postpone our discussion on other sampling-related topics. The question of how one obtains all required metrology data on one wafer in a manufacturing environment will be addressed in a future publication.

In line Electrical measurement (E-Test) are the most effective predictors for EOL yield control. As technology progress with scaling, the number. of process layers increases, allowing in-line electrical measurements only after several months since lot started process in-line. As a result, each E-Test monitor controls longer and more challenging process loop. Most of the in-line pattern control that impact electrical performance measured separately for each pattern polygon and material properties. In addition, Edge Placement Error (EPE) methodology, allows combination of multiple dimensions like CD, Overlay and LER measurements to better predict yield impact. Technology shrinkage, resulting that transistor electrical performance, defined by more geomaterial parameters as well as material compositions and defectivity. In this paper we demonstrate a direct prediction from high resolution Scanning Electron Microscope (SEM) images to the first inline electrical measurement (M1) using Deep Learning (DL) techniques. The DL model provide early prediction of electrical performance, describing accurately Within Wafer (WIW) variation weeks earlier than the actual electrical measurements. Multiple layers prediction may indicate suspected process loop that modulate majority of variation and save time to solution. It can be achieved since the DL model utilizes complementary information exist on the full e-Beam image like materials and defectivity. The following results will indicate that accumulating information collected from several layers will improve prediction sensitivity and lead to even more accurate prediction capabilities. We assume that the effectiveness of the proposed prediction method will increase with process complexity, since the modulation of the existing yield predictors is losing sensitivity as design rule shrinks. In addition, since fabrication phase gets longer, the time to actual electrical measurements increase, making an early, nondestructive, and accurate prediction for electrical performance more and more valuable.

With the continuous shrinking of semiconductor device nodes, the reduction of on-product overlay (OPO) becomes extremely critical for high-yield IC (Integrated Circuit) manufacturing. This requires accurate overlay (OVL) process control which can be better achieved by using an optimized OVL target design and a more advanced metrology platform. The novel rAIM® imaging-based-overlay (IBO) target, which has a grating-over-grating structure with significantly smaller pitch sizes as compared to the standard advanced-imaging-metrology (AIM®) target, can improve OVL measurement accuracy by adopting a more device-compatible design with high Moiré sensitivity. This paper demonstrates the advantages of rAIM targets by comparing and quantifying their performance to standard AIM targets through key parameters including raw OVL, residuals, precision, and total measurement uncertainty (TMU). We also present the performance of rAIM targets on different OVL metrology platforms. We conclude that with an optimized target design and an advanced OVL measurement platform, rAIM targets can be an ideal overlay metrology solution for advanced dynamic random-access memory (DRAM) devices.

The concept of using contours from SEM images for improving metrology results on semiconductor manufacturing applications exists for almost over two decades. However, the usage of contours was limited due to the difficulties encountered while identifying the contours and their consistency to be combined with traditional metrology results. As the technology for detecting contours advanced, so did the challenges, with higher levels of noise, lower contrast, more complex shapes, multiple layers combination, and tighter specifications. More recently, with the high level of sophistication attained by contour metrology, different applications and needs in different fields can be addressed by it. One of the most powerful benefits of using contour metrology is the possibility of combining information coming from the image to a layout, augmenting the metrology capability, pattern intent control and pattern quality. This work presents different strategies for obtaining contours from SEM images as well as multiple applications that are now relying on contours for either improving existing capabilities or proposing new ones that enable processes to continue to advance in future technology nodes.

We are beginning projects to validate the physics models used for interpretation of electron microscopy images. In one of them, we will measure electron yields and energy spectra from cleaned well-characterized samples subjected to electron bombardment inside of a spherical retarding field analyzer in ultra-high vacuum. In another, we will measure the same features, lithographically patterned on free-standing Si membranes, with measurement techniques that differ in their interaction physics. A modeling project will compare measurement results with simulations using existing and new models. Good models should predict the observed yields and produce agreement among measurement techniques.

CD-SEM is one of the workhorse metrology tools for evaluating the patterning performances in the semiconductor industry. With the continuous shrink of device feature sizes, measurement uncertainty, of such devices should improve accordingly, including tool-to-tool matching. Great efforts are made in fabs to ensure matching between CD-SEMs. Basically, there are two approaches : tool matching based on statistical CD measurements and tool matching based on physical tool parameters. The first methods require long recipe run on each tool for data collection while the second methods require dedicated maintenance tool time. In parallel, the emergence of SEM contour metrology brought new opportunities, for example in OPC modeling, process assessment or overlay metrology. Recently, a step has been made to demonstrate that offline SEM contour metrology can be matched with standard CD-SEM. In this paper we evaluate the possibility to use SEM contour metrology to perform a remote CD matching on images coming from two different CD-SEM. A large set of patterns of various dimensions and shapes (both 1D and 2D) is imaged with two different CD-SEM after etch process step. For each image the contours are extracted using a remote software. A matching model is calibrated to match contour measurements of the same pattern imaged with the two CD-SEMs. The matching model can be calibrated using either one or both inline SEM measurement or using additional metrology data (typically AFM measurement or any reference metrology measurement). The matching model parameters include both parameters for the contour extraction calibration and measurement matching parameters. Two modeling approaches are compared : one matching model averaging multiple measurement matching sites and a multiple (per pattern type) contour calibrations/ measurement matching sites model. These different matching models are assessed using as main metrics the remaining CD difference between SEM contour measurements on images coming from the two CD-SEM (ΔCD_matching) and TMU analysis. We show that an overall ΔCD_matching variability of 0.6 nm and a TMU below 2 nm can be obtained with the dataset. We evaluated a strategy to achieve matching of two CD-SEM using a remote contour extraction solution and a matching model.

We investigate the limits of characterizing extreme ultraviolet (EUV) patterned features, highlighting Critical Dimension Scanning Electron Microscopes (CDSEM) and E-beam massive metrology techniques. Due to local CDU variation from EUV stochastic variations, there is increased need for multiple measurement sites in CDSEM or enlarged fields of view (FOV), leading to an increase in measurement time. Massive ebeam metrology techniques provide a robust method for imaging more features within a larger field of view. We assess the trade-off between accuracy and throughput in determining global and local CD variation. Via data sets, with matched parameters for each tool set will be analyzed at different process points to obtain local and global CD variation for statistical analysis of both techniques.

In this work, important use cases for HV-SEM will be explored by simulation, such as HAR hole / trench imaging with various profiles and depths, buried feature imaging to understand detection and effective resolution with depth for optical overlay cases, and buried defect and void detection, using a new improved electron beam simulator which greatly extends utility of JMONSEL, AMAG SimuSEM, enabling many complex simulation scenarios to be achievable with many improved outputs and other augmentations. The use of simulation designed experiments (DOEs) to predict best conditions and performance for the above applications will be demonstrated, along with some physical validation in the HV-SEM process space for the JMONSEL/SimuSEM physics kernel by reproducing a few cases in the literature and to experimental results on recent AMAG7 HAR measurement targets.

High integration of semiconductor processes is being made to realize high performance in miniaturized chips. The performance of a semiconductor chip may vary depending on target variables such as thickness, line width, shape, composition, and physical properties of each layer constituting the chip. Therefore, in order to secure chip performance, accurate detection of target variable values and quality control are required, and it is necessary to check in advance for defects that may occur during the process. Optical inspection technology is widely used in the semiconductor metrology field due to its advantage in that it can detect defects in the wafer at high speed by scanning the wafer with a light source having a specific wavelength band. However, in recent years, the size of defects caused by high integration and miniaturization of semiconductor chip processes is getting smaller, and thus there is a limit to detecting micro defects using conventional optical methods. In this study, we propose an algorithm to improve the defect detection performance by utilizing multi-scan images acquired under various conditions. Using the suggested algorithm, it was confirmed that the SNR (Signal to noise ratio) of the defect of interest was improved by about 99%, and the classification performance for noise was improved by 4 times.

Non-destructive metrology for photomasks and wafers has always been an important requirement for semiconductor lithography, and with the advent of EUVL, enabling further shrinkage of semiconductor devices, the challenges in this field have increased significantly. Coherent diffraction imaging (CDI) is a promising alternative to standard imaging for EUV photomask actinic inspection. EUV light can also be used for wafer inspection to benefit from the resolution improvement allowed by its short wavelength. In order to perform lensless imaging for patterned wafers, however, we need to probe the sample surface at grazing incidence to ensure a sufficiently high reflectance. The EUV reflective grazing incidence nanoscope (REGINE) at the Swiss Light Source was develped to perform grazing incidence lensless imaging for patterned wafers. REGINE is a tool that combines CDI, scatterometry and reflectometry in the photon energy range between 80 to 200 eV, and at the grazing incidence angle of 1 to 28 degrees. In this work, we will present the latest characterization of our system, and preliminary results.

An innovative metrology technique has been devised to address current limitations of optical critical dimension (OCD) in advanced semiconductor metrology. This technique is based on multiple self-interferometric pupil imaging, called Mueller matrix self-interferometric pupil ellipsometry (M-SIPE). The system integrates an innovatively designed interference generator in both illuminating and imaging optics, allowing for the massive acquisition of full polarization information across entire angles around the device. The vast amount of information can offer fully comprehensive structural analysis, accomplishing enhanced sensitivity and the ability to break the well-known parameter correlation issues. The system employs a single-shot holographic measurement technique on the pupil plane, enabling rapid acquisition of three-dimensional spectral information, such as wavelengths, incidence angles, and azimuth angles. Thus, unlike conventional OCD tools, M-SIPE can obtain multi-angular and full polarization information without any mechanical movements. We verified the performance of M-SIPE by the experiment of non-patterned wafers of various conditions using an optical testbed. Our results confirmed good agreement between the experiment and theoretical simulations across all angular ranges. Furthermore, the actual device simulation was conducted to show sensitivity enhancement and ability for breaking the parameter correlation issues. The results confirmed that the large amount of angular information from M-SIPE technique could overcome current metrological challenges.

In recent years, the number of manufacturing processes is increasing in pursuit of device pattern miniaturization. Complicated processes such as SAQP have been introduced, increasing the number of control parameters. Nevertheless, the demand for production yield enhancement is as high as ever. To detect CD changes, fixed-point measurement by using CD-SEM or scatterometry tools is typically performed, but these time-consuming measurement methods are not suitable for high-density, across-a-wafer measurement or for detecting CD anomalies that randomly occur. To address these issues, we have developed a technology that enables high-precision CD measurement of more than 100,000 points per wafer within a few minutes. It enables monitoring various CD defects in various processes such as holes and L/S patterns after photolithography, L/S patterns after SAQP/SADP, and fine hole diameters after etching. It can also measure CD imbalances after SAQP processes. In addition, it enables precisely obtaining intra-shot CD distribution based on the distribution over the entire surface of a wafer. We evaluated this technology using actual device wafers. CD imbalances of SAQP on DRAM process wafers were measured, within a few minutes across a wafer, at an accuracy of |X|+3σ<0.5 nm. CD changes at the outermost area of the wafer were captured by CD measurement of 27 nm hole patterns on a DRAM process wafer. Random CD defects were captured by CD measurement of 38 nm hole patterns on a DRAM process wafer. These defects affect device yield but were not detectable by using conventional inspection tools.

As High Numerical Aperture Extreme Ultraviolet Lithography (High NA EUVL) gets ready to step in the integrated circuit manufacturing (ICM) world, more and more work is being devoted to ensuring that all the elements involved in the process, from materials to equipment, will be ready to meet the required specifications when the time comes. One of the most critical pieces in such an ecosystem is the photoresist (PR), the material used to accurately transfer the design to the wafer. In the last years we have observed the introduction of various effective alternative approaches, such as dry metal oxide photoresist. PR always had to meet daunting specifications in terms of resolution, roughness, and sensitivity. However, in the brave new world of High NA EUVL, this is not enough. In fact, as the size of the printed features shrink, it is essential to limit the aspect ratio to avoid pattern collapse. Furthermore, the larger NA will reduce the Depth of Focus (DOF), thus requiring the use of ultra-thin resist films. The direct consequence of that is that the resist thicknesses used nowadays will not be suitable for High NA EUVL, where target thickness is expected to drop down to 20nm or less. Such a dramatic reduction in thickness has the potential to negatively impact, beside printing performances, the quality of the metrology and inspection as well, as discussed in our previous work. In the present work, we study the effects of reducing thickness in the case dry resist using various metrology and inspection techniques, such as Critical Dimension Scanning Electron Microscope (CDSEM), Atomic Force Microscopy (AFM), and e-beam defect inspection. As resist thickness decreases, noise level and image contrast are expected to be reduced, with a potential negative impact on the quality of the CD measurements both in terms of accuracy and precision.

The semiconductor industry continually evaluates new materials to improve the process or minimize product variability, which could create measurement challenges for metrology tools in the visible and near-infrared (NIR) spectrum. Opaque materials (i.e., ‘hard masks,’ ‘HM’) are placed in between the resist (i.e., inner layer) and process (i.e., outer layer or underlying layer) in 3D NAND or DRAM processes to control the etch of high aspect-ratio structures to maximize product yield. However, longer wavelengths (e.g., IR WL) may be required to penetrate and properly view the underlying process layer and measure OVL accurately. In this work, longer wavelengths will be evaluated to improve measurement accuracy and keep up with the increasing use of opaque materials, which is expected to increase in future nodes. We will review the benefits of IR WL to OVL measurement accuracy by quantifying the OVL residuals, contrast precision (CP), and total measurement uncertainty (TMU) on multiple DRAM and 3D NAND critical layers.

We present a tabletop EUV imaging reflectometer that can characterize the geometry and composition of nanostructures. The setup can be operated in multiple modes — intensity reflectometry, scatter-reflectometry, or imaging reflectometry depending on the length scales and periodicity of the nanostructures present. All these modes of metrology can be performed non-destructively and in a lab-scale setup, using a tabletop high-harmonic coherent EUV source.

EUV resist is prone to damage (shrinkage) caused by electron irradiation during dimensional measurement using electron beam tool, such as CD-SEM. High repeatability and low shrinkage is demanded for metrology. In this study, we propose solutions that can reduce shrinkage and maintain performance of repeatability. We evaluated shrinkage of EUV resist using 100V low energy electron beam. Comparing to 300V electron beam, 100V beam enabled to shrinkage. Meanwhile, repeatability improvement was achieved by multiple proprietary solutions.

This conference presentation was prepared for SPIE Advanced Lithography + Patterning, 2023.

To enable the “endless progression of Moore’s law” [1], traditional scaling has moved from sufficient to a mere necessary condition. In other words, the concrete implementation of high-NA EUV lithography remains among the top R&D priorities of the semiconductor industry for the coming years. However, the roadmap predicts that other scaling boosters, all putting a strong emphasis on the third – vertical - dimension, will also play a critical role in allowing increased functionality from a fixed surface area of Si. In this presentation, we first review the challenges imposed on metrology and inspection by 3D devices in the context of GAA, 3DIC and 3D memories. We then discuss our work extracting buried information of various nature, i.e. dimensional, overlay and defectivity, using less conventional metrology. Finally, we recommend stronger focus on 3D see-through metrology to ensure the readiness of metrology as devices move deeper into the 3D era. [1]L. van den Hove, SPIE ALP (2022)

Several next generation integration schemes – e.g. for 3D stacked transistors, backside power distribution, and advanced packaging involve permanent wafer bonding steps and drive to sub-10nm overlay requirements post bonding. Distortion during wafer bonding is a major determinant of best achievable overlay between post to pre bonding lithography layers. Here, we investigate correlations between wafer bonding process and post bonding overlay performance through a combination of experiment and modelling. We use a custom test vehicle to collect wafer distortion data from pre- and post-bond processes, as well as overlay data after the post-bond processing steps (anneal and thin). The results establish direct relationships between incoming wafer distortion, bonder-induced distortion and post-bond lithography overlay to a pre-bond level. We also use the experimental results to validate a wafer bonding simulation model to further physical explanation of process-induced distortion. The experiment results will enable advanced wafer bonding process controls to optimize distortion and scanner overlay to meet technology targets. The results will also help guide hardware design to improve distortion fingerprints to best improve scanner overlay, as well as address the distortion challenges from incoming wafers.

Here, we explore the application of Mueller Matrix Spectroscopic Ellipsometry (MMSE) based scatterometry to determining the shape and dimensions of vertical nanowire gate-all-around (GAA) transistors. These transistors could be used in memory applications, like 4F2 3D NAND. The simulated sensitivity of MMSE based scatterometry to changes in the geometry of GAA transistor test structures was characterized at a critical etch back process step to define gate length. MMSE scatterometry simulations were done using rigorous coupled wave analysis (RCWA). We also searched for the optimum azimuthal measurement angle that increases the information available in off-diagonal Mueller matrix elements. A correlation study was done between the etch back height and nanowire diameter critical dimensions to determine if the Mueller matrix response could be isolated to changes in one parameter. The vertical GAA structure was shown to have an isotropic MMSE response at azimuthal measurement angles of 0, 45, and 90 degrees. The simulations show that MMSE scatterometry is sensitive to changes in the structure such as etch back thickness and diameter of the nanowire. These two parameters gave unique Mueller matrix responses, which can be monitored individually. In this simulation study, the nanowire structure was shown to have a differentiable Mueller matrix response for changes to key parameters.

Global semiconductor packaging manufacturers are developing advanced process technologies with the rapid rise of heterogeneous packaging and 3D packaging. High-aspect-ratio (HAR) structures like through silicon vias (TSV) or redistribution layers (RDL) that come with the prevalence of 3D packaging technology have further significantly increased the difficulties in optical critical dimension (OCD) metrology. Due to emerging technical challenges, effective sub-micron HAR OCD solutions are highly demanded to resolve the technical bottleneck. Thus, This article presents an AI-guided method for simulating and building a training dataset using the finite difference time domain (FDTD), then forming a DNN model for reconstructing CDs. At the same time, an optical scatterometry-based microscope was developed to adopt optical light capable of penetrating a sub-micron opening size structure and characterizing critical dimensions such as top critical dimension (TCD) and depth. In the optical system design, the optical FOV can be narrowed down only to cover a single sub-micron structure for OCD metrology. A preliminary test verified that a single sub-micron structure with an aspect ratio of 1:3.3 and the maximum bias between the measured data and the SEM references could be kept within a few tens of nanometers for its depth, TCD, and BCD measurement.

Wafer bonding is a key technology for many advanced chip technologies. For 3D integration, advanced stacking schemes and high-density packaging put a stringent requirement on the bonding reliability. Bonding quality can be characterized by the absence of voids at the bonding interface, as the voids delimit the complexity of the subsequent processing and integration steps. Therefore, in-line and non-destructive inspection techniques for void detection are crucial for early-stage detection and full process integration. In this work, we perform a comprehensive study on bonding void detection for 3D integration. We fabricate bonded Si wafers with programmed bonding voids with size from 10 nm to 20 μm. We combine different inspection and review tools, including acoustic, optical, electron beam etc., for bonding void detection at different process steps of the fabrication with different top Si thicknesses.

Patterning defect metrology requires data interpretation with classification, each well-suited to machine learning (ML). Defect classification however has notable misclassification costs; mislabeling a defect as nominal has greater impact than the converse. Though quantified costs are not publicly available, total economic misclassification cost (total cost) is optimized across orders-of-magnitude variation in cost ratio C and classification threshold 0.01 < τ < 0.99. Convolutional neural networks are trained using the intrinsically weighted and scaled asymmetric focal losses (AFL, sAFL) with hyperparameter γ with weighted and unweighted binary cross-entropy (wBCE, BCE) functions trained for comparisons. Optimal functions and conditions are identified for reducing total cost. For reproducibility, publicly available ML data sets are surrogates for industrial imaging data. For these data the sAFL mimimizes total cost at τ = 0.5, C ≥ 16. The AFL reduces total cost at 0.1 ≤ τ < 0.5, C > 128. Asymmetric loss functions lower total cost versus wBCE by 15 % to 40 % for 0.2 < τ < 0.5, C < 64. Total economic misclassification cost can be tailored using asymmetric focal losses. Estimations are presented to allow the extension of reported trends to industrial applications with strong class imbalances between defect-indicative and nominal-indicative data.

Low-noise CD-SEM images are required in order to obtain robust and reliable measurement results, especially for complex 2D patterns. However, standard practices to reduce CD-SEM noise during image acquisition (increasing number of frames, increasing beam current, etc.) also increase acquisition time and the probability of deteriorating the materials under inspection. This effect is getting further attention of the industry on the case of EUV (extreme ultraviolet) resist, being an electron sensitive material and presenting small thickness, requiring extra care in order to prevent damage. Although there are techniques that intrinsically improve the metrology robustness to noise (such as model-based contour extraction), denoising SEM images may prove useful and a complementary approach for further improve metrology quality in such challenging cases. In this work we propose an innovative solution using Deep Learning Neural Network (DLNN) for low frame image denoising, which performs the model calibration using low frame images only, from a reduced dataset. A specific data augmentation approach is used in order to limit the number of images needed for the training. The denoising performance of the algorithm was evaluated in terms of accuracy and precision over a synthetic dataset, not used during the training of the neural network. The results show an improvement both in precision (up to 50% on the extreme case, 5% on average) as well in accuracy (over 13% on average).

There is a growing need for accurate depth measurements of on-chip structures. Since Scanning Electron Microscopes (SEMs) are already regularly being used for fast and local 2D imaging, it is attractive to explore the 3D capabilities of SEMs. This paper presents a comprehensive study of depth estimation performance when single- or multi-angle data is available. The research starts with an analytical line-scan model to show the major contributors of the signal change with increasing height and angle. We also analyze Monte-Carlo scattering simulations for height sensitivity on similar structures. Next, we validate the depth estimation performance with a supervised machine learning model and show correlation with the previous studies. As predicted by the sensitivity studies, we show that the height prediction greatly improves with increasing tilt angle. Even with a small angle of 3 degrees, a threefold average performance improvement is obtained (RMSE of 16.06 nm to 5.28 nm). Finally, we discuss a preliminary proof-of-concept of a self-supervised algorithm, where no ground-truth data is needed anymore for height retrieval. With this work we show that a data-driven tilted-beam approach is a leap forward in accurate height prediction for the semiconductor industry.

We developed imaging spectroscopic reflectometry (ISR) based on hyperspectral imaging and deep learning and built it as an in-line facility. After obtaining the reflectance as a hyperspectral cube of the 350 – 1100 nm wavelength region throughout the whole device wafer, dimension of the nanometer-sized structure can be imaged through the supervised learning model. In particular, by including near-IR region in the spectrum, the bottom critical dimension (BCD) of the high-aspect ratio structure such as channel hole (CHH) of the 3D NAND evaluated in this study can be imaged non-destructively and rapidly. After removing the top through decapsulation, the actual BCD was measured by SEM and was linked to the hyperspectral cube to construct a supervised learning model. The BCD predicted through ISR showed a correlation of R²=0.72 with the actual BCD. In addition, the shape of the defect on device chip caused by insufficient etch at the bottom of CHH, obtained by ISR was identical to the inspection image taken after decapsulation. Compared to spot measurement, ISR shows the advantage of being able to capture defects that occur at random locations in the device wafer. From our high volume sample of 3D NAND, ISR result showed a high correlation (R² = 0.82) with the rate of failure caused by channel hole while the conventional spot measurement showed only R² = 0.41. By using ISR, we could optimize the etching process for the wafer edge area where CHH formation is particularly weak.

An AI-assisted computational method is developed to achieve superresolution imaging by overcoming the limitations of optical imaging caused by the diffraction limit. The method builds and fits a parametric optical imaging model by resolving an inverse problem. Highresolution imaging often requires a high-magnification lens, but this reduces the field of view. The transfer function of the imaging system is parameterized using diffraction theory and simulations of real imaging disturbances. "Known sample" and corresponding "Measured image" pairs are used to train the model and fit the real transfer function of the system. A deconvolution algorithm is applied to resolve the reverse problem and maintain high resolution under an enlarged field of view. The spatial resolution can be improved by 2.33 times compared to the diffraction limit. This method is useful for semiconductor critical dimension metrology in automated optical inspection.

The semiconductor manufacturing process is becoming more complex and time-consuming due to smaller design rules and denser patterns, which inevitably leads to an increase in the number and types of defects. In the past, considerable efforts have been made to classify defects, and this has been implemented at the equipment level. However, in order to enhance the efficiency and productivity of semiconductor process development by automatically classifying random, systematic, and parametric defects according to various process schemes and structures, there is a need for a deep learning-based automatic defect classification technique with a higher degree of freedom and utilization. In this study, we used not only scanning electron microscope images, which have been actively studied, but also optical inspection images at various scales. Deep learning algorithms were evaluated for various layers of memory devices to select the optimal algorithm for each layer, and an accuracy of 94% or more was achieved, even with a small sample size (under 1000), which is critical in the R&D stage. It is expected that this technique will be able to spread and be applied to more diverse layers in the future. By providing faster and more diverse classifications of defects in semiconductor manufacturing processes and ensuring higher consistency through continuous sample size expansion, it is anticipated that this technique will contribute to shortening the development period and improving yield.

Due to their increasingly complex 3D geometries, upcoming gate all around (GAA) devices pose new metrology challenges for which there is not yet any established HVM metrology solution, in particular for various critical timed etch steps [5]. Soft x-ray (SXR) scatterometry using 10-20 nm wavelength light is a promising next-generation metrology technique for 3D profile metrology and overlay (OVL) applications. This wavelength regime offers unique benefits over existing metrology techniques today: (1) Short wavelengths allow for higher resolution measurements than traditional visible wavelengths could offer, enabling measurement of structures at device pitches. (2) Primarily single scattering yields low correlation between parameters and aids physical interpretation of signals. This enables many parameters of interest to be extracted accurately and simultaneously. (3) SXR provides 3D capability, with stack heights up to 400 nm supported and high depth resolution due to the broadband source and sensor. These properties together make SXR suitable for measuring the 3D profiles of advanced devices such as gate all around (GAA) transistors, as well as after develop (ADI) overlay at device pitch. In this paper, we demonstrate SXR for profile metrology of GAA devices. We show sensitivity to average SiGe lateral recess etch depth as well as individual nanosheet critical dimensions, which cannot be reliably accessed by other nondestructive, inline metrology techniques available today. We furthermore demonstrate sensitivity in ADI OVL measurements directly on device-pitch structures in the presence of an underlying patterned nuisance layer.

X-ray fluorescence techniques in special operation modes can provide valuable quantitative insights for semiconductor related applications and can be made compatible to typical sizes of homogeneously structured metrology pads. As their dimensions are usually in the order of several 10 μm per direction, it must be ensured that no adjacent regions are irradiated or that no x-ray fluorescence radiation from adjacent areas reaches the detector. As this can be realized by using small excitation beams, a multitude of information can be retrieved from such XRF data. In addition to elemental composition, including sensitivity to sub-surface features, one can derive quantitative amounts of material and even dimensional properties of the nanostructures under study. Here, we show three different approaches for studies related to semiconductor applications that are capable to be performed on real world dies with commonly sized metrology pads.

Critical Dimension (CD) control is essential in the semiconductor industry and becomes more challenging as photolithography limits keep getting pushed to reach technological nodes smaller than 10 nm. To ensure quality and control of the processes, it becomes necessary to explore new metrology techniques. In this sense, Critical Dimension Small-Angle X-ray Scattering (CDSAXS) has been identified as a potential candidate to determine the average shape of a line grating with a sub-nanometric precision. In this paper we benchmark the CDSAXS results to Optical Critical Dimension (OCD), Critical Dimension Scanning Electron Microscopy (CDSEM) and Transmission Electron Microscopy (TEM) measurements previously collected from industrial metrology tools at manufacturing line and in characterization laboratory. Emphasis is placed on the model used for CDSAXS and how to improve it. We discuss the differences between all these multi-scale and multi-physics techniques, and question our capacity to compare them.

We present a reconstruction of the in-depth profile of line gratings using critical-dimension grazing incidence small angle x-ray scattering with a compact Cu-Kα x-ray source mounted on a laboratory SAXS. By taking advantage of the grazing-incidence configuration and with a rotation of the gratings under the x-ray beam, several orders of the Bragg rods were probed and lead to the extraction of the in-depth profile of the lines. The extracted in-depth profile is compared with 3D-AFM results. The methodology developed mimics the one of CD-SAXS measurements, in transmission, in order to enable future comparison between the two approaches as well as building complementary modeling. These results open new perspectives for x-ray metrology at the fab since the Cu-Kα x-ray source is the most developed, spread and used source by the x-ray community.

EUV scatterometry can retrieve geometrical information from nanoscale grating structures through elastic scattering of EUV radiation and the evaluation of the diffraction intensities. Its geometry and energy range place it in between grazing incidence x-ray scattering (GISAXS) and optical critical dimension (OCD). PTB recently commissioned a new scatterometry setup for the EUV and soft x-ray region that can address sample areas below 100 × 100 μm size by using a comparably steep, grazing angle of incidence of up to 30°. At the same time, the full cone of exit angles of 30° can be detected such that also the higher orders can be recorded in scatterometry measurements. It has been commissioned at PTB’s monochromatic soft x-ray beamline at the synchrotron radiation facility BESSY II and can also be used for simultaneous x-ray fluorescence detection. Its great tunability and energy resolution allows to scan across absorption edges of the relevant semiconductor materials to increase the contrast between different materials. The nanoscale geometry of modern transistor designs features different materials and structure sizes in the single digit nanometer range. Using the information wealth of spectrally resolved scatterometry measurements from the new setup, we present data and first geometrical reconstructions of selected, complex, industry-relevant design studies. The geometrical reconstruction of these structures relies on precise measurements, modelling of the scattering process, and statistical data evaluation methods.

In order to minimize wafer loss and increase productivity, it is important to predict the wafer yield drop caused by defects in early manufacturing stage. In conventional yield prediction method, the chip failure was manually checked using images sampled by defect inspection. However, it is insufficient to predict yield accurately since the prediction was performed with only a few sampled defect images. Furthermore, the kill-ratio per defect was not estimated properly because the electrical properties were not considered in predicting a failure such as short or open. In this paper, we propose a new yield prediction method using defect and layout information with the following two characteristics. We tried to overcome the existing sampling limitations by using the defect inspection raw data that contains the coordinates and size information of all defects. In addition, we matched the electrical signal information of the layout pattern with silicon directly and then calculated the kill ratio per defect. The kill ratio per defect has doubled from 30% to 70% applied to sub-20nm Emerging memory devices. And we have confirmed that the yield prediction gap, which is the difference between the predicted yield and the actual yield, decreases from 31% to 8%. It is expected to reduce wafer loss about 10% in Emerging memory devices and same improvement will occur in other products such as DRAM, FLASH, and LOGIC devices by applying this sophisticated methodology.

E-beam inspection based on voltage-contrast defect metrology has been widely utilized for failure mode analysis of memory devices. Variation in E-beam image contrast indicates shorts, opens and void defect inline inspection in the idle of production line. Meanwhile, accurate measurement of threshold voltage and the source-drain current is required to characterize memory cell through multi-layers. However, in the subthreshold region of memory cell, voltage contrast (VC) is weakened due to gate voltage stimulated by electron dose of e-beam scanning. We developed a modulated beam imaging with the SEM vector scan system to enhance VC contrast and defect inspection capability. Reliability of the modulated electron microscopy is validated by comparing with physical probing test result for process variation of Boron doping and annealing conditions in full wafer processing. VC with the modulated electron microscopy is well correlated to the probing test result. Image contrast of the modulated microscopy can differentiate contact via on floating circuit and disconnected floating circuit. We applied the modulated electron microscopy for in-line electrical defect detection at the middle of manufacturing line of integrated circuits. The defect distribution map by the modulated electron microscopy was confirmed to reproduce the physical probe test result. By achieving in-line electrical characterization before back end of line, yield loss issues can be detected and characterized two weeks earlier than conventional method. Moreover, this ability to detect and characterize memory cell issues inline is supposed to contribute to overcome the yield learning cycle bottleneck.

Process window qualification using focus-exposure wafers is an essential step in lithography and a key use case for CD-SEM metrology. An automated analysis using the correlation between CD and focus/dose is easily possible but rarely done due to missing safety checks. Pattern fidelity that is analyzed by eye and problematic focus/dose conditions that may cause pattern degradation are excluded by hand. Specifically, when EUV lithography is utilized for exposing the most critical layers, roughness estimation becomes much more important, as it will restrict the process window further. We develop and describe unbiased and stable roughness estimates for contact hole patterns and integrate them into the process window analysis pipeline and inline monitoring routine. The analysis goes beyond simple roughness values and can detect a variety of possible CD-SEM measurement problems and shape deviations as well. Furthermore, we introduce a novel image-based machine-learning approach to detect outliers and quantify defective or abnormal patterns. Notably, the underlying model does not require knowledge of the types of CD features or design information for which outliers should be detected. We demonstrate that the approach can reliably detect local defects and a variety of other pattern anomalies. Using the generated visualizations, images with anomalous features can be flagged automatically and the locations of the defects or deviations are pinpointed. The approach yields not only the final missing piece in automated process window qualification, but also new opportunities to monitor pattern fidelity in lithographical semi-conductor processes.

This conference presentation was prepared for SPIE Advanced Lithography + Patterning, 2023.

As design rule of device shrinks quickly, process controls of HAR (high aspect ratio) buried defect become very crucial. In the past, monitoring of this defect mostly depended on e-beam inspection and destructive inspection. These methods cost a lot and need more time to prepare. So, optical inspection has been requested continuously. However, there are several technical obstacles, such as severe noises from under layers and quantification of defect height. In this study, we developed novel depth quantification technique for HAR structure. By using this new technique, we drastically improved (x240% higher) sensitivity of not-open defect. Light budget was rigorously analyzed and optimized for best SNR. To design deliberate non-destructive height quantification technique, we are currently working on development of TSOM (Through-focus Scanning Optical Microscopy) technique for HAR defect.

Semiconductor complexity continues to increase with each new process node as the industry pushes the limits of 2D logic and DRAM scaling using EUV lithography and transitions to intricate 3D architectures including Gate-All-Around (GAA) transistors, high-aspect ratio DRAM and 3D NAND memories. This complexity creates significant challenges for process engineers. Defects become much more critical and difficult to detect as chip patterns shrink, the use of 3D structures proliferate and the number of layers increases. The ability to detect and characterize tiny, buried defects in emerging logic and memory chip designs is surpassing the imaging capabilities of conventional eBeam technology. In short, you can’t fix what you can’t see. This is where cold field emission (CFE) technology comes in. Long regarded as the optimal eBeam technology, CFE operates at room temperature, resulting in narrower, higher-energy electron beams that produce higher resolution and faster imaging speed compared to conventional thermal field emission (TFE) technology which operates at temperatures exceeding 1,500 degrees Celsius. Process engineers can tune the CFE eBeam system for maximum resolution or they can lower the resolution to match that of TFE but with significantly faster imaging speed. The pictures below illustrates the resolution and speed differences between CFE and TFE. Until now, use of CFE-based systems has been limited to lab environments because the stability of the eBeam column was insufficient for the stringent requirements of high-volume semiconductor manufacturing. One of the main factors affecting stability is the cleanliness of the eBeam column. All eBeam systems contain an extremely small source tip that emits the electrons used for imaging. Because the tip is so small, any contamination – even a single atom – can potentially disrupt the flow of electrons and cause system instability. In TFE systems, the source tip is so hot that it automatically repels any contaminants that might gather on the surface. In contrast, the room temperature operation of CFE, which is the main driver for its higher performance, makes cleaning much more challenging. To bring CFE technology out of the lab and into the fab, Two innovations that solved the CFE stability challenge. The first was creating an extreme ultra-high vacuum inside the eBeam column that is well below 1 x 10-11 millibar, which is two to three orders of magnitude better than for TFE systems and nearly the vacuum level found in outer space! Through an extensive optimization process, an extreme ultra-high vacuum was combined with specially developed chamber materials to greatly reduce the presence of contaminants inside the eBeam column. Even under extreme ultra-high vacuum, a tiny amount of residual gas can still exist. If gas molecules adhere to the electron source, performance is significantly degraded. The second innovation we developed is a cyclical self-cleaning process that continuously removes contaminants from the CFE source, thereby enabling stable and repeatable performance for high-volume manufacturing environments. Bringing CFE eBeam technology to high volume chip making manufacturing took more than 10 years of intense development of a CFE defect review and defect inspection platforms. By enabling chipmakers to discover defects they’ve never been able to see before, faster, CFE is helping accelerate the development and production of advanced process nodes.

As semiconductor devices continue to introduce new materials and structures, not only the dimensions but the material properties are becoming important in determining the device properties. Properties of insulator films used in transistors and memory devices, such as breakdown voltage and damage, are of particular interest as they determine the characteristics as well as the reliability of the devices. To ensure efficient production of these devices, an inline tool for metrology and inspection of material properties is desirable. One way to evaluate the material properties is to measure the material’s response to application of voltage. For this purpose, we have developed laser-assisted SEM; an SEM with laser irradiation capability to control the electrical state of the material under SEM observation. The laser can be used to inject carriers into insulators and neutralize insulator charging caused by the electron beam. By evaluating the energy of secondary electrons, we measured the charging voltage of insulators, defined as the difference in the surface potential between when the laser is irradiated and not irradiated. Similarly to breakdown voltage, we verified that the charging voltage increases with the insulator thickness. Furthermore, charging voltage was shown to be dependent on damage due to plasma in an etcher. Therefore, charging voltage measurements assisted by a laser is a unique way to evaluate the material property of insulators. We believe our laser assisted SEM will open the door to new types of electrical and material characterizations and go beyond the traditional role of SEMs in metrology and inspection.

The transistor architecture of complementary FET (CFET) is attractive for scaling down in technology nodes beyond 1 nm. CFET comprising vertically stacked nMOS and pMOS can be integrated monolithically and sequentially. The monolithic process is cost effective but complex because it requires patterning of high-aspect-ratio (HAR) structures and vertical edge placement control for stacked n-p nanosheet channels. It also brings challenges to in-line metrology in measuring the vertical dimension. In this work, we demonstrate a non-destructive, in-line metrology solution to measure the etch-back depth by CD-SEM. As the backscattered electron (BSE) signal intensity at the bottom of an HAR structure is determined by the structure's depth and top dimension, the depth can be monitored via an index based on the grey level and top dimension in CD-SEM images. Wafers with different etch-back depths were measured for evaluation of the M0 etch-back process in CFET integration. Good agreement was obtained between the etch-back depths measured by CDSEM and TEM. The flexible capability of CD-SEM to measure the depth and variation from extremely small areas to the wafer level could be helpful for CFET process control.

High voltage scanning electron microscopy (HV-SEM) has recently been adopted as an on-device overlay metrology tool. However, the chip-manufacturing industry requests more advanced tools capable of low-distortion imaging and versatile measurement functionality for multi-layer processing. We developed a high voltage e-beam inspection (HV-EBI) tool for on-device overlay metrology that fills the abovementioned requirement. The HV-EBI tool has the capability of variable acceleration voltage in the range of 30kV to 50kV and wide field of view (FOV) imaging up to a maximum of 50μm with extremely low first-order distortion in the level of <0.01% and 0.1mrad and uniform in-plane beam perpendicularity. In this paper, we demonstrate the performance of on-device overlay measurement by using the proposed HV-EBI tool combined with enhanced die-to-database (D2DB) algorithm and image processor.

Devices based on 2D material channels require high-quality monolayer material. However, although the value of many laboratory metrology techniques has been demonstrated on small coupons, the development of inline characterization of 2D material layers grown on full 300mm wafers is still missing. In this work, we evaluate and combine different inline metrologies to characterize at wafer level the thickness and the morphology of tungsten disulfide (WS₂) layers grown on full 300mm wafers. Combining the results from the different techniques allows us to reveal the morphology and the thickness of the WS₂ layers as well as their uniformity across the 300 mm wafers for different growth conditions.

As the measurability (sampling capacity, measurement coverage, and measurement speed) of metrology systems are being enhanced to keep pace with the evolution of semiconductor manufacturing processes, the detection of defective areas and hidden weak patterns by analyzing the massive measurement data is becoming significantly important. In this study, we propose new methods to detect defective areas and hidden weak patterns by mathematically processing massive measurement data. By applying the methods we propose, we were able to successfully detect the hidden weak signals of the millimeter scale in the wafer.

The W-Recess step for 3D NAND replacement gate process currently has no in-line process control solution. W replacement renders the structure opaque in the ultraviolet/visible/near-infrared (UV/VIS/NIR) region beyond just a few tier layers in the most advanced 3D NAND devices. Additionally, increased word line (WL) slit pitch scaling further reduces the already minimal optical signal from the top of the structure. Through finite-difference time-domain (FDTD) and optical critical dimension (OCD) simulations, we show that a specially designed, design rule-compliant (that is, possessing a slit pitch matching the device) ellipsometry target permits mid-IR light to completely penetrate through oxide metal (OM) pairs, enabling measurement of the W-Recess Z-profile. Furthermore, recent experimental data measured on the designed target in >200 pair 3D NAND node prove that mid-IR light has sensitivity to the slit bottom. An OCD model was developed and showed good design of experiment (DOE) discrimination capability and reference correlation.

As DRAM technology continues to evolve, advanced nodes shrink the device dimensions and raise the requirements for on-product overlay control to reduce residual error. Increased process complexity also demands tighter accuracy and robustness in metrology control, which necessitates new and innovative metrology enhancements and methods. Scatterometry-based overlay (SCOL®) metrology is a unique overlay metrology architecture that uses angle-resolved pupil imaging for overlay analysis and calculation. KLA’s SCOL metrology system offers wide-spectrum tunable laser and multi-wavelength (MWL) illumination patterns along with custom-designed advanced algorithms that provide multiple measurement conditions to meet unique layer and target requirements. This paper demonstrates improved overlay metrology accuracy and residual error on DRAM FEOL critical layer with SCOL technology. Multiwavelength and rotated quadrupole (RQ) illumination in the metrology tool are utilized to provide significantly improved residuals compared with the traditional single-wavelength (SWL) and on-axis illumination.

With the extreme ultraviolet (EUV) lithography and its pitch scaling, the resist shrinkage from electron beam has returned to an important critical dimension (CD) control issue - unlike multi-patterning where the smallest CD is larger than 40nm. The resist height reduces to maintain the aspect ratio below 2:1 which is critical factor for the prevention of the resist collapse. This leads to huge challenges to minimize the shrinkage of resist during the scanning electron microscope (SEM) measurement. Accurate and precise metrology of chemically amplified resist (CAR) type EUV photoresist processed pattern utilizing classical beam energy for lithography pattern such as 500V is great challenging as electron beam exposure of 1st measurement already fully shrunk the pattern. Moreover, occurrence of carbonization along with shrinkage hinders finding best conditions for not only metrology optimization but also minimized process impact. In this work, we evaluated the magnitude of shrinkage of CAR type EUV photoresists with several approaches including 0th and 1st shrinkage estimation utilizing line & space pattern and contact hole pattern as a function of landing energy dose and static/dynamic repeatability method to distinguish behaviors of shrinkage and carbonization by controlling interaction time of photoresist to its environment. One approach to trace minimized 0th shrinkage and metrology uncertainty in lithography process is utilizing 1st shrinkage (1st CD – 2nd CD) analysis together with plotting absolute value of the 1st CD as a function of dose. The other approach to trace optimization condition was comparing exposed area with electron beam and non-exposed area achieved by comparing litho/etch consecutive process on the same area. Furthermore, model fits, a simulation study were also performed.

Current SEM target design methodology relies on knowledge and experience with previous designs. This experience-based method can break down in cases of significant architectural or material changes, requiring a “best guess” approach for a new target. Validation of this guess is only available once wafers are created and measured. Using electron interaction simulations in the target design process enables waferless evaluation of targets. Simulations can also identify the necessary imaging conditions to generate a high-quality SEM image, indicating the required tool conditions for successful metrology. The work in this paper demonstrates a correlation between simulation and results on wafers.

In semiconductor chip manufacturing, dedicated metrology targets are used for measuring overlay (OVL) between layers after the lithographic process step. Until recently, overlay targets have had typical dimensions of 20x20 microns, but have been reduced in size to allow for more critical product real estate. Reducing metrology target size, however, increases optical crosstalk and diffractions from the target’s edges which can introduce significant errors in the reported OVL values. In this work, we will evaluate the following parameters: 1. The beam spot shape on the metrology target 2. The best target design under size/wavelength constraints 3. Improved OVL extraction algorithm We will present the hardware and software optimizations for experimental measurements taken over a cascade of targets. While decreasing the target’s size, we quantified the OVL measurement performance via dynamic precision, tool-induced shift (TIS), and results through focus (Z position). We will demonstrate how these optimizations enable the measurement of targets as small as 6x6 microns without compromising throughput or measurement quality.

The measurement process is important in managing semiconductor device yield, which is affected by the availability of measurement equipment such as critical dimension scanning electron microscopes (CD-SEMs). Here, decreasing CD-SEM availability is caused by measurement errors when inappropriate measurement recipes are used. To improve CD-SEM availability, we developed a machine-learning-based error analysis method to identify error causes and x measurement conditions by using accumulated CD-SEM data. However, a single error analysis model can be applied to only a single semiconductor product because different semiconductor products have different data distribution even if they use the same recipe. Additionally, manufacturers often modify recipes every few months. As a result, an error-cause analysis method needs to be able to easily adapt to new recipes. Therefore, we developed a three-stage method that consists of error detection modeling, feature scoring, and error cause estimation on the basis of high-scoring features. Because we found the top scoring features do NOT change as the feature distribution changes when the error causes are the same, the error cause estimation on the basis of high-scoring features enable to be applied to different semiconductor products and new recipes. We evaluated our method with actual operational data, and estimated error causes that often correspond with the results of manual analysis by skilled engineers.

As the semiconductor industry rapidly approaches the 3nm lithography node, on-product overlay (OPO) requirements have become tighter, which drives metrology performance enhancements to meet the reduction in overlay (OVL) residuals. The utilization of multiple measurement wavelengths in Imaging- Based Overlay (IBO) has increased in the past few years to meet these needs. Specifically, the color per layer (CPL) method allows for optimizing the OVL measurement conditions per layer, including focus, light, wavelength (WL), and polarization customization which enhance the metrology results. CPL is applicable for multiple technology segments (logic, foundry, DRAM, 3D NAND), relevant for different devices (DRAM high stack layers, NAND channel holes, etc.), and can work well for both thin and thick layers for standard and EUV lithography processes. In this paper, we will review the benefits of CPL for multiple DRAM and NAND critical layers. We will describe how CPL can contribute to measurement accuracy by quantifying the OVL residual reduction in comparison to single-wavelength (SWL) measurement conditions.

Run to Run systems for lithography are taking a critical place in the process control ecosystem ^[1] as the industry is pushing towards advanced nodes and tight specifications. As multivariate algorithms with context decomposition provide reactivity, adaptability, and monitoring efficiency, they can be limited by the feedbacks declared in the R2R model. Especially in lithography overlay where various machines can have different behaviors depending on layers and reticles. Adding to this complexity, the specificity for overlay is that it is always measured to a reference, that measure can be impacted by the reference process conditions and signatures can also propagate through the layers. In case of events on reference machines it is essential to be able to apply different process corrections depending on various lot history. Different process conditions were also found to be required for different products depending on tool couples (process/reference) to meet mix and match performance requirements. In such a configuration, classical feedback effects composing the multivariate R2R loops also need to evolve in concatenated effects, to be able to model coupling components not modeled until then. This work has been done at ST, in a high mix logic fab where many different technologies coexist on the same tooling, increasing complexity for APC control.

3D-NAND manufacturers are racing to increase the storage capacity by increasing the number of stacked layers. As the increase of the number of stacked layers, complex process, films stress and deep-etch tilting effects were observed to affect the device overlay control significantly. Traditional optical overlay metrology via scribe-lane image based overlay (IBO) has its constraint to entirely reflecting in-device overlay behavior because of the differences on pattern density, film stack and stress to memory array. In this study, Patterned Wafer Geometry (PWG) tool was adopted to collect wafer shape step-by-step. The in-plane deviation (IPD) and Gen4 overlay derived from wafer shape was used as efficient indexes to distinguish which metrology is representative of indevice overlay for critical layers. High voltage scanning electron microscope (HV-SEM) and optical scatterometry critical dimension measurement (SCD) were adopted separately combining with traditional scribe-lane IBO metrology for in-device overlay improvement through applying non-zero offset (NZO) overlay compensation at different photo layers.

An InGaN photocathode with a negative electron affinity (NEA) surface is suitable for industrial use because of features such as a long quantum efficiency lifetime, availability with a visible laser as an excitation light source, and the presence of a transmission-type structure. The first objective is the development of an InGaN photocathode electron gun that can be mounted on a scanning electron microscope (SEM) and the evaluation of the electron beam size at the emission point, maximum emission current, and transverse energy of the electron beam, which are important factors for realizing a high probe current in the SEM. The second objective is the evaluation of emission current stability, while the third objective is the generation of a pulsed electron beam and multi-electron beam from the InGaN photocathode. The parameters of the electron beam from the photocathode electron gun were an emission beam radius of 1 μm, transverse energy of 44 meV, and an emission current of up to 110 μA. Using a high beam current with low transverse energy from the photocathode, a 13 nA probe current with 10 nm SEM resolution was observed with 15 μA emission. At 15 μA, the continuous electron beam emission for 1300 h was confirmed; at 30 μA, the cycle time between the NEA surface reactivations was confirmed to be 90 h with 0.043% stability. Moreover, a 4.4 ns pulsed e-beam with a 4.7 mA beam current was generated, and a 5 × 5 multielectron beam with 12% uniformity was then obtained. The advantages of the InGaN photocathode, such as high electron beam current, low transverse energy, long quantum efficiency lifetime, pulsed electron beam, and multi-electron beam, are useful in industries including semiconductor device inspection tools.

We have evaluated two types of high aspect ratio (HAR) structures of semiconductor memory devices by adopting small-angle x-ray scattering in transmission geometry (T-SAXS). One is the thin TiN thickness on the sidewall of 1.4 μm deep holes. The results indicate that T-SAXS is capable of determining sidewall thickness profiles with sub-nanometer accuracy. The other is the precise three-dimensional shape of 4.2 μm deep holes. The results show that the shape of the hole cross-section parallel to the sample surface changes drastically in the depth direction. These evaluation results of the two structures are consistent with that of transmission electron microscope, respectively.

As wafer process complexity increases, demand for precise overlay accuracy including measurement of wafer deformation in advanced photolithography processes has increased. In general, wafer deformation can be measured with high accuracy by obtaining wafer alignment position information at multiple sites on a wafer. However, when a photolithography exposure system is used to perform the necessary wafer alignment measurements to improve overlay accuracy, the productivity of the exposure system will be drastically reduced due to the increase in total alignment measurement time. Canon developed the stand-alone wafer metrology tool (MS-001) as a solution to improve the overlay accuracy and the productivity of semiconductor manufacturing. MS-001 is used to perform Feed Forward Alignment (FFA) correction in which the wafer deformation is measured before the wafer is transferred to the exposure system and the data is sent to the exposure system. This reduces the number of alignment measurements required in the exposure system, making it possible to combine high productivity with high overlay accuracy. MS-001 also features improved selectivity of measurement marks by image detection and enhanced selectivity of measurement wavelengths by a new alignment light source unit (Hi-ALS). These allow MS-001 to select the optimal measurement mark and wavelength according to the wafer process. In addition, it has become possible to monitor process changes as well as alignment. In this paper, we demonstrated the performance of MS-001 and overlay accuracy improvement by FFA correction using DRAM product wafers. And we also verified the feasibility of a wafer monitor function using MS-001 to detect wafer deformation occurring in the manufacturing process. These results show that MS-001 can solve the challenges posed by complex processes. These results indicate that MS-001 has the potential to solve challenges caused by complex processes.

Apart from the ever-continuing lateral scaling in the xy-plane to increase the transistor density, additional new concepts find their way to the semiconductor industry too. These concepts are based on making more use of the third dimension. One relatively simple idea would be to create a second layer of transistors to double the transistor density. However, the material requirements are high and the quality of the layer deposition by conventional Chemical Vapor Deposition (CVD) techniques is insufficient. Another application to free up real estate, enabling a smaller cell size and hence an increased transistor density, is to power-up the transistors from the backside. The power rails for logic devices are historically defined in the first Metal layer and consume quite some space. Bringing the power rails to the backside will free up space. However, access to the transistor layer from the backside of the wafer is far from trivial due to the presence of a 775-μm thick silicon substrate. The answer to the challenges mentioned above is wafer-to-wafer direct bonding. Although this technique is not new and already widely used in the semiconductor industry to manufacture CMOS Image Sensors (CIS), it currently finds its way to the high-end logic markets. In case of layer transfer, a crystalline silicon layer is created by bonding a Silicon-On- Insulator (SOI) wafer to the already existing device wafer. After the bonding step, the substrate of the SOI wafer will be removed leaving the crystalline silicon layer behind. Access to the transistor layer from the wafer backside can be enabled by wafer-to-wafer bonding as well. To this end, a completed device wafer will be bonded to an (un-patterned) carrier wafer. The substrate of the original device wafer will be removed, enabling access from the backside. Wafer-towafer bonding applications can only be enabled in case the induced wafer deformations are low or when they can easily be corrected during the subsequent exposures on the scanner. At CEA-Leti, a dedicated test vehicle process flow has been developed to characterize the wafer bonding-induced distortion fingerprints for both the layer transfer and the backside power delivery network applications. The wafer process flow has been simplified without losing the industry relevant on-product overlay challenges. Wafers have been created to enable an extremely dense characterization of the wafer bonding induced fingerprint. The methodology we applied enables us to isolate the wafer bonding induced distortion fingerprint, something that is difficult to do in a production environment. The Back-Side Power Delivery Network (BS-PDN) application is the most challenging one. The initial raw measured wafer distortion fingerprints are around 60 to 80-nm. These numbers can already be easily brought down by scanner corrections to ~15-nm (mean+3σ) without too much effort. However, these numbers are too large for the 2-nm technology node and beyond, and further improvement is required. The goal of this paper is to present the path forward to bring the bonding induced wafer distortion levels to 10-nm and below. We show the capability of the latest and greatest EVG bonding tool hardware and recipe settings available at the time of running the experiments in combination with the correction capability an ASML 0.33NA scanner.

The field of object detection using Deep Learning (DL) is constantly evolving with many new techniques and models being proposed. YOLOv7 is a state-of-the-art object detector based on the YOLO family of models which have become popular for industrial applications. One such possible application domain can be semiconductor defect inspection. The performance of any machine learning model depends on its hyperparameters. Furthermore, combining predictions of one or more models in different ways can also affect performance. In this research, we experiment with YOLOv7, a recently proposed, state-of-the-art object detector, by training and evaluating models with different hyperparameters to investigate which ones improve performance in terms of detection precision for semiconductor line space pattern defects. The base YOLOv7 model with default hyperparameters and Non Maximum Suppression (NMS) prediction combining outperforms all RetinaNet models from previous work in terms of mean Average Precision (mAP).We find that vertically flipping images randomly during training yields a 3% improvement in the mean AP of all defect classes. Other hyperparameter values improved AP only for certain classes compared to the default model. Combining models that achieve the best AP for different defect classes was found to be an effective ensembling strategy. Combining predictions from ensembles using Weighted Box Fusion (WBF) prediction gave the best performance. The best ensemble with WBF improved on the mAP of the default model by 10%.

As the cell size of memory devices continues to shrink, tighter on-product overlay (OPO) specs require more accurate and robust overlay control. The overlay error budget mainly consists of the reticle, scanner, process, and metrology errors. The metrology budget is generally required to be <10% of the OPO control budget so that the accuracy and robustness of overlay metrology become more crucial as pattern size gets smaller on current 1x nm DRAM nodes. For overlay control in high-volume manufacturing (HVM), the primary optical overlay metrology typically used is Image-Based Overlay (IBO). In many cases, scatterometry overlay (SCOL), using a direct grating-scanning method, was shown to achieve more accurate After Development Inspection (ADI) overlay measurements. Using a tunable source and customized illumination pupil to directly scan within the grating cell, this technology improves accuracy by reducing the contribution of pattern surroundings in the scribe line, resulting in improved OPO control stability. Since the purpose of overlay control is to minimize actual device pattern misregistration, as measured after the etching process (AEI), achieving accurate and stable characterization of the systematic deviation between ADI and AEI overlay known as Non-Zero-Offset (NZO) is critically important. Accurate NZO applied to the scanner via the Advanced-Process-Control (APC) loop enables effective scanner overlay control at the post-lithography ADI step. This paper demonstrates a new scatterometry overlay technology adopted in DRAM use cases that resulted in OPO and NZO stability improvement. In addition, we demonstrate an efficient method to monitor HVM run-to-run overlay performance and NZO stability by comprehensive dataset modeling combining ADI and AEI.

An absolute alignment measurement of an underlayer and overlayer of overlay mark enables an innovative overlay control by which each layer’s grid errors can be independently corrected, versus of a conventional relative overlay measurement and control. We demonstrate an absolute alignment measurement of stacked overlay marks such as Diffraction-Based Overlay (DBO) by adopting a unique method incorporated in a standalone, image-based alignment metrology system. An alignment accuracy of each layer is evaluated using product wafers by comparing alignment measurement result to the reference data. In conclusion, we were able to achieve R²>0.97 coefficient.

We investigate on how to improve the performance of thickness determination from the optical scatterometry spectrum using machine learning. Our investigation is focused on a specific application for thick layered structures for 3D NAND with oxide/nitride repeating pairs. Since fast determination of thickness of every layer or detection of any outlier is not very efficient with the regression analysis using an optical model-based calculation due to requirement of a huge amount of calculations along with many parameters, machine learning (ML) can be applied for this application pursuing a faster solution. However, we also need to achieve its precision and accuracy as good as possible under a limited amount of ML train data sets. In order to carry out an efficient extraction or selection of features from data which is very important for improved performance of ML, we applied Fourier analysis of spectrum and investigate on how ML performance is improved.

Understanding the electromagnetic properties of the 3D through silicon via (TSV) with high aspect ratio is important for the 3D IC stacking and packaging. The electromagnetic simulations were used to explore the TSV with different model parameters, such as top critical dimension, bottom critical dimension, hole depth, sidewall slope, sidewall roughness, curvature of the base, and light wavelength. A model is proposed to parameterize TSV structure features. The simulation results corresponding to these model parameters are discussed.

Mask tape-out is a frequent job in wafer fabrication factories and research institutes. Frame generation is one of the important steps in mask tape-out flow. It requires extensive lithography, process integration, and mask tape-out experience; a large amount of manual work and various data preparation is included, especially when multiple products are combined into a single mask and all product conditions need to be fulfilled simultaneously. When more factors need to be considered, mistakes can be made. We develop a methodology to help frame generation, such as alignment and overlay mark design, selection and placement. It has demonstrated the ability to guide people in error-proofing work, support for frame GDS automatic generation and metrology recipe automatic generation. This is a user-friendly methodology that can reduce the frame generation difficulty and generation time from several weeks to a few minutes.

In semiconductor industry, depth measurement is usually performed using the optical critical dimension (OCD) metrology, the atomic force microscopy (AFM) and transmission electron microscope (TEM). However, there are some limits in the depth measurements using OCD metrology or AFM. Therefore, this paper presents a new monitoring method for local depth using scanning electron microscopy (SEM) and a feasible verification method using AFM. This paper considers monitoring of local hole depth for the direct contact (DC). First, this paper proposes a depth monitoring index based on gray level (GL) of SEM image. The index includes not only the GL of the hole but also the GL of the background to reduce the effect of the GL inconsistency. Second, this paper verifies the effectiveness of the proposed depth monitoring index using in-FAB AFM. The reliability of the in-FAB AFM measurements as the reference for local depth is verified by TEM.

Scribe line width reduction and high-order scanner correctibles are driving overlay (OVL) target size reduction. Shrinking imaging-based overlay (IBO) target size for standard target types, such as AIM® or BiB, is not possible without a performance impact. In this paper, new target layouts and supporting OVL tool setup methods will be explored to enable small OVL targets to meet performance, accuracy, and robustness requirements. Two approaches have been explored: (1) measuring smaller grating pitches utilizing oblique illumination, and (2) measuring targets not obeying 180° rotational symmetry requirement (half-targets). Each of these approaches allows shrinking conventional imaging OVL target area by a factor of two. Evaluation results are reviewed in this paper and further target size reduction is presented.

The scanning electron microscope (SEM) with photocathode technology was launched by retrofitting the photocathode electron gun to a commercial-based SEM system. In this SEM system, the excitation laser for photoelectron generation from the photocathode is synchronized to the scanning signal. SEM images were obtained by high-speed modulation of the photoelectron beam current using the photocathode SEM, where the location in the field of view and its irradiation current were arbitrarily selected on a pixel-by-pixel basis (Selective e-Beaming technology). As a demonstration experiment contributing to non-contact electrical inspection, low-voltage SEM imaging of MOS-FET structures in 3D-NAND flash memory was performed using this selective e-beam technology. As a result, changes in the voltage contrast of the drain electrode were observed in response to on/off selective electron beam irradiation to the gate electrode in the MOS-FET structure. As an extension of the selective electron beaming technology, a Yield Controlled e-beaming (YCeB) technology was invented to control the secondary electron yield generated in the entire field of view of the SEM image by feedback control of the laser power irradiating the photocathode to the intensity of each pixel in the SEM image. The YCeB image, in which the laser power intensity corresponding to the probe intensity is modulated so that the secondary electron yield generated in the entire field of view of the SEM image is constant, is a clearer image with less noise than the original SEM image.

Edge detection is the core of most metrology tools to identify boundaries between materials. With the shrinking in size of all devices for higher performances, this task becomes more and more challenging. In addition, the use of new composition of materials increases the challenge by reducing the contrast between different materials. The general quality of the images is critical to recover the right edges, in particular for High Resolution Electronic Microscopy, which remains the reference for high quality metrology during R&D phases. In these images, the low contrast of the edges and changes in the texture of the materials creating no sharped borders are impacting the performances of classical edge extraction methods. In order to improve capacities of algorithms, we propose a pipeline to generate edge maps. These edge maps can be further used in more classical algorithms to extract better measurements. Two versions of the pipeline can be used, a first one trained on generic images from the semiconductor industry and a second one that can be tuned on specific use cases. The first one provides a ready-to-use solution and the second one is able to provide more accurate measurements at the cost of annotating images. To illustrate these results, we demonstrate the use of these features with various algorithms on use cases from the semiconductor industry such as gates and wires. We propose comparison between the two pipelines both in term of accuracy and time to recipe.

As the dimensions of nanostructure rapidly shrink, the optical critical dimension (OCD) metrology, owing to its fast, non-destructive, and in-line-compatible features, has proved to be an effective tool to detect 3D periodic structure’s geometry at several nanometer-scale [1]. When the integrated circuit manufacturing enter the 3 nm technology node, Complementary FET (CFET) architectures, by utilizing shared gate for vertically stacked nanosheet n-FET and p-FET, have achieved notable reduction on average cell area, metal length and block-level area [2]. Because many metallic layers are not transparent to most optical wavelengths in CFET structures, and the gate oxide thickness and uniformity, the metal gate and inner spacer dimension uniformity are crucial during the process control [3], the sensitivity and precision of OCD metrology are very important and challenging. For instance, the inner spacers are formed by Atomic Layer Deposition (ALD) of spacer material on the recessed pockets of the SiGe superlattice formed by lateral over-etch during the source and drain etch process.The inner spacers insulate the metal gates and the source/drain terminals, which are decisive to the gate reliability and parasitic capacitance. Therefore, accurate control and measurement for inner spacers’ dimension uniformity is crucial to the manufacturing. In this paper, we will perform a study on the critical dimensions in CFET structures by using optical scatterometry simulation based on Rigorous Coupled Wave Analysis (RCWA). By tuning detection parameters, such as angle-of-incidence, illumination wavelength, polarization and scattering orders, we try to find an optimized parameter settings for measurement, and give recommendations for building OCD models of CFET structures.

Advanced technology nodes require tighter lithography overlay specifications with higher throughput and lower cost of ownership. Today, with the accelerating complexity of nanoelectronics for memory applications, an increased emphasis is placed on controlling the on-product overlay (OPO) budget. Consequently, accurate in-die overlay measurements play a critical role after the etching process (ACI) for which it can better reflect the actual product overlay. Here we propose a solution with the combined spectroscopic full Mueller matrix, measured with the KLA next-generation SpectraShape™ dimensional metrology system and a physics-based machine learning algorithm. Both real spectra collected by the SpectraShape and theoretical spectra generated from the scatterometry model are trained against their corresponding ground truth reference and synthetic reference data respectively to predict overlay. Theoretical and experimental results show that the Mueller elements are sensitive to very small changes in the overlay parameters which can enable inline, high-throughput overlay metrology. Accuracy, robustness, and precision on massive datasets using design of experiments (DOE) wafers are presented and discussed. Moreover, the measurement reliability is assessed with a key performance indicator (KPI), designed to flag a process excursion in a high-volume manufacturing (HVM) environment. Good agreement is observed between the KPI and the actual model accuracy.

This study aims to improve defect detection and optimize deep learning models for wafer surfaces. Deep learning methods for high-yield wafer processes often suffer from insufficient sample size. The challenge of generating enough defective samples hinders the model's ability to accurately detect defects through training. This study resolves the issue by using a generative adversarial network style transfer method to generate synthetic data in batches and flexibly determine the location of defect generation. The optimized model achieved an accuracy reduction of only 2% and a 55% reduction in inference time. Edge computing was also applied for online, real-time detection of defects.

Defect inspection is an important part in the semiconductor manufacturing. This task is tedious and time consuming if done manually. Therefore, reliably automating this task is a major challenge for many semiconductor manufacturers. In the recent years, deep-learning methods for object detection have demonstrated ever better performances. However, most of the publicly available models are trained on natural images and objects. Hence, most of them needs a long and data greedy training step to be used on industrial Transmission Electron Microscopes or Scanning Electron Microscope images. In this context, we propose a deep-learning based model to detect and segment defects in electron micrographs. Using SmartDef3 from Pollen Metrology, we annotated defects on images from several industrial applications. We split them in a training and validation dataset, with which an Instance segmentation model with state-of-the-art backbone is trained. The model is then evaluated on different use cases. Competitive performances on new data in terms of detection rates and segmentation quality are demonstrated and discussed. Furthermore, the model showed a relevant defect detection rate even on images that are not in the semiconductor domain, providing an interesting tool for defects detection on a new use case without new training data. This shows how deep learning strategies can help save time and costs by automation of defects inspections. Furthermore, advanced metrological analysis of the defect can be simultaneously obtained that help optimizing the manufacturing processes and reduce defect production rate.

In excimer laser operation, the maintenance choices by the field service engineer are critical to maximize laser performance while minimizing laser downtime, part replacement expenses, and overall touches to the instrument. To optimize maintenance choices, the engineer must estimate future internal performance of the laser, the impact of each consumable part and their interactions, the impact of operational settings and their interactions, and the optimal timing for each maintenance event. To aid engineers’ decision-making, a deep learning-based laser simulator was developed. The simulator forecasts and plots laser performance under one or multiple maintenance scenarios where each scenario may each have different maintenance timing and multiple maintenance operations such as parts replacement and other operational choices. The simulator is based on a deep recurrent neural network (RNN) with a seq2seq encoder-decoder architecture. Through the encoder, this architecture leverages model inputs that include historical laser performance and configuration data in a temporal dependence structure. Through the decoder, the architecture also captures temporally specific information about future laser operation. By adjusting the decoder inputs, the model forecasts can be altered to reflect future laser maintenance scenarios under consideration. The RNN is deployed in a software plugin for Fabscape® which provides a graphical user interface with interactive elements for field service engineers to forecast, compare maintenance operations, and compare maintenance timing on future laser performance. Ultimately, by simulating the impact of maintenance through the deep learning model and GUI, field service engineers can gain insights to enhance proactive maintenance and plan upcoming service events.

The complex vertically stacked gate-all-around (GAA) manufacturing process drives the demand for more challenging inline metrology requirements. GAA technology with specific technical requirements starts from the first process step, 1) the superlattice, where the multi-stack Si/SiGe pairs must be grown defect-free with matched Si nanosheet thicknesses, and %Ge per layer, sharp interfaces, and a minimized subsequent thermal Ge diffusion across the stacks. More critical steps, among others, are the 2) partial recess of the sacrificial SiGe layers that precede 3) the inner spacers which prevent a channel to source/drain short circuit and reduce the parasitic capacitance, and 4) the channel release process at the “remove poly gate” module, where the SiGe is selectively removed before the high-k metal gate. Driven by tight performance control, a sheet-specific metrology solution is highly desired at each of the above four critical steps. The ideal solution for such an application is non-destructive, precise, accurate, and highly productive. In this paper, a scatterometry critical dimension (SCD) solution for the GAA sheet-specific measurement from various GAA structures is presented. The SCD solution includes an advanced and optimized full Mueller Matrix spectroscopic ellipsometry in conjunction with a physics-assisted machine learning (ML) algorithm. Additionally, the best methodology to address the solution's robustness to process variation is described and presented. It will be shown that an optimized signal-to-noise ratio combined with ML can provide a superior optical metrology solution to the growing challenge in GAA applications.

An etching process for high-aspect ratio (HAR) structure is one of key technologies in the recent semiconductor device fabrication. In the development and control of etching processes, it is very critical to evaluate depth, shape profile, and tilting. Critical dimension small angle X-ray scattering (CD-SAXS) is a powerful measurement technique to characterize such shape parameters of HAR structures. In this paper, we evaluated the measurement sensitivity of CD-SAXS for changing shape parameters (average CD, depth, side wall shape, tilting) of HAR holes using simulation results. The simulation results show that CD-SAXS has sufficient sensitivity to characterize shape parameters of HAR structures. We also demonstrated the performance of CD-SAXS by measurement of 1μm depth holes on the 300 mm wafer. As a result, we were able to obtain detailed hole profiles, distribution of average CD and tilt angle across the entire wafer.

In this paper, we propose an unique metrology technique for the measurement of three-dimensional (3D) nanoscale structures of semiconductor devices, employing imaging-based massive Mueller-matrix spectroscopic ellipsometry (MMSE) with ultra-wide field of view (FOV) of 20×20 mm². The proposed system enables rapid measurement of 10 million critical dimension (CD) values from all pixels in the image, while the conventional point-based metrology technique only measures a single CD value. We obtain Mueller matrix (MM) spectrum by manipulating wavelength and polarization states using a custom designed optical setup, and show that the proposed method characterizes complex 3D structures of the semiconductor device. We experimentally demonstrate CD measurement performance and consistency in the extremely large FOV, and suggest that the combination of MMSE and massive measurement capability can provide valuable insights: fingerprints originated from the manufacturing process, which are not easily obtained with conventional techniques.

Two of most important parameters for the integrated circuit manufacturing are linewidth and overlay. The linewidth uniformity is guaranteed by good exposure tooling, photoresist material, photomasks, Optical Proximity Correction (OPC), optimized patterning process, and good metrology. The linewidth metrology utilized the Scanning Electron Microscope (SEM) directly, which accuracy is entirely determined by the equipment. The overlay metrology quality, however, not only depends on the equipment performance, but can also depend on the substrate quality. There are two types of overlay measurement techniques, i.e., the Image Based Overlay (IBO) and the Diffraction Based Overlay (DBO). In this paper, we will focus our study on a 3 nm Complementary FET (CFET) metal layer overlay. The dimensions of a 3 nm logic design can be as small as 20~24 nm for the Fin Pitch (FP) and 36~48 nm for the Contacted Poly Pitch (CPP) and a On Product Overlay (OPO) of 2.5 nm is required. We will report our study on the DBO for the metal to metal overlay under typical 3 nm logic CFET design rules and a proposed film stack.

In advanced integrated circuit manufacturing technology, the introduction of nanosheet, forksheet, and Complementary Field Effect Transistor (CFET) architectures has created very complicated and dense vertical structures with dimensions as small as several nanometers and with many metallic layers which are not transparent to most optical wavelengths, posing a serious challenge to the metrology. We have provided a scatterometry study on a test pattern design based on the 3 nm logic design rules. Through a simulation study on typical dimensions, we have investigated various linewidths and contact depth with an algorithm based on the Rigorous Coupled Wave Analysis (RCWA).

In addition to the conventional process control method like dimensional metrology, there is a growing need to measure the electrical characteristics of device structures. Detection of defective electrical characteristics during device fabrication is important to improve device yield and shorten the ramp-up time of the manufacturing process. Voltage contrast of traditional scanning electron microscopes can be used to measure some of the electrical characteristics but is limited in its sensitivity and, hence, its applicable processes. We have developed a Laser-assisted SEM (LA-SEM) with (1) laser irradiation function and (2) electron beam modulation function to control and enhance the voltage contrast (VC) for in-line electrical inspection and measurement. In this report, for samples with high-impedance components obstructing the view of defect of interest, we confirmed that ultraviolet laser irradiation provides defect contrast that cannot be obtained with electron-beam-only VC. For Not-Open defects on a PN junction, the VC was improved by a factor of 1.19 by using a laser in the near-infrared region. Furthermore, to extract electrical properties of defects and monitor their changes during the manufacturing flow, a VC circuit simulation function was developed to quantitatively estimate VC transients obtained by modulated electron beam irradiation. As an example, a quantitative estimation of RC by transient voltage contrast analysis was performed on floating plugs with varying resistance using metal film deposition on its side walls. A decent correlation between the estimated electrical properties and the sheet resistance of the metallic film was demonstrated.

Driven by the continuous decrease of the length scales of fabricated semiconductor structures, ultraclean semiconductor processing equipment suffers more and more from contamination with nano- and micrometer sized particles, which may be introduced in such systems from the outside via gas flows either externally injected or through translational and/or rotational (robotic) feedthroughs. One promising approach to filter contaminating particulates from these gas flows is the application of a plasma particle seal in which airborne particles carried by a gas flow pick up free charges from a plasma and then are deflected by an externally applied electric field in the plasma’s afterglow region. Consecutively, these contaminating particles may be guided to less harmful locations in the system or even be fully removed. In this contribution, we present measurements that reveal the importance of additional drag forces imposed on the particles and the influence of these drag forces on the particles’ trajectories when the plasma is operated in pulsed mode.

As overlay requirement is getting tighter, a litho user needs to dedicate a specific scanner to print the critical layers for recent DRAM node to prevent Matched Machine Overlay (MMO) penalty. But periodic scanner maintenance is unavoidable in scanner operation over long period, and it can cause “Dedication Break”. Although lens calibration, one of the most important scanner maintenance processes, is necessary to minimize lens aberration which has drifted over time, the resulting aberration change can cause an overlay impact on the wafers in the process. This impact can be greater than normal MMO penalty. In the worst case, the user should block the wafers in process due to serious overlay impact which comes from aberration change. In order to prevent the case, users gradually reduce the flow of wafers in the dedicated mode to reach the zero dedication right before lens calibration. Then, new dedication mode can start insert after lens calibration to avoid “Wafer in Process (WIP) Impact” for all dedicated scanners. Such a manipulation can take several months resulting in loss of cost and throughput. Here, we introduce an WIP impact simulation method before lens calibration based on physical theory, ASML lens emulator and process information; pattern design, illumination pupil, dose and metrology layout. If user can define the pattern shift result for each bottom layer (before lens calibration) and top layer (after lens calibration), potential overlay WIP impact is predictable and user can selectively decide wafer and lot operation plan to minimize cost and throughput loss per scanner. In addition, user can monitor and prepare countermeasures for potential WIP impact in advance.

In the field of semiconductor manufacturing, the precise alignment of patterns on a wafer die is critical for the proper functioning of the resulting integrated circuit. However, various factors can cause deformation of the die, which can result in overlay errors and negatively impact device performance. In this work, we focused on the development of die nanotopography metrology, which is used to investigate the topography evolution of five selected dies over several process steps. The impact of manufacturing steps as film deposition, annealing and CMP on die shape deformation and its relation to different pattern densities is measured using optical interferometry. We show that full-die nano-topography measurements are able to detect stress-induced in-plane die distortions as an effect of different annealing processes on SOI or silicon-bulk substrates.

In modern nano-scale lithography, an essential role of the source, the illumination, and projection lenses is to deliver the precise amount of energy at a specific wavelength to the photoresist deposited on a wafer surface during exposure. Unfortunately, the source of the most advanced lithography processes may produce unwanted infrared components passing through the illumination and projection lenses and reaching the wafer surface. These infrared residues can cause local heating resulting in deformation of the optical elements and the exposed wafer, thus causing deterioration of the image quality. Some infrared spectrum components are in the band from 2 μm to 12 μm. An infrared detector that can measure only these spectral components of the exposure beam, without being affected by the much more powerful exposure spectral component, is helpful for optics diagnostic purposes and improving imaging quality. In this paper, an ultra-thin uncooled integrable-on-chip linear array infrared detector to measure the band of 2-12 μm infrared radiation is designed and fabricated based on the photovoltaic multiple junction heterostructure from VIGO Photonics, made of a HgCdTe narrow bandgap semiconductor. Features such as zero bias, low noise, and fast response, together with a wide active window, make the detector unique for use in the mid-infrared band. Besides lithography applications, the new detector can be useful in testing, inspection, and equipment using infrared sources such as: He-Ne lasers (0.6 to 4 μm), STEAM lasers (2 to 200 μm), CO₂ lasers (5 to 11 μm), InGaAsP lasers (0.8 to 3 μm), and PbSnTe (3 to 20 μm) and PbSnSe (7 to 40 μm) lasers.

In this study, we present an automatic defect classification (ADC) application for outgoing quality inspections. In most outgoing inspections, all of the defects were manually classified to reject or accept the inspected die with the defect classification. Earlier adoption of ADC systems usually emphasizes both accuracy (recall) and purity (precision) as output metrics to deploy the system to classify the defects. In our implementation, purity is targeted as the main output metric for the classification of clearly defined defects in the training set. This allowed us to deploy an automatic defect classification solution with high purity and benefit from its automatic classification earlier in the adoption process with an immediate impact on workload reduction, while progressively tuning performance on less pure defect classes. Overall, higher than 80% purity levels are achieved on more than 75% of the population of all the defects assigned for classification. Several ad-hoc monitoring systems; such as time-window based statistical tests and subject-matter-expert (SME) based performance of ground truth, are implemented for the continuity of the performance of the classifier.

In recent years, Deep Learning (DL) algorithms employing artificial neural networks (NN) have been shown to be a powerful tool for the classification and quantification of images including intensity data from various x-ray scattering techniques. These algorithms generally require massive, labeled datasets for training and validating the NNs. Such datasets can be extremely difficult to obtain from measurements for several reasons. The size of the dataset is limited by the variation in available samples and the time available to measure the samples. The labels are limited by both the number and quality of available reference measurements. In this work we will discuss the use of DL for the analysis of critical dimension small angle x-ray scattering (CD-SAXS) data from high-aspect ratio (HAR) structures encountered in 3D NAND and DRAM memories. We have developed a novel solution for the automatic generation and labeling of large synthetic datasets using “realistic simulations” of the x-ray scattering data. Our solution includes instrumental artifacts such as background scattering and Poisson noise normally found in real x-ray images. Additionally, we have included structural variations based on parameters obtained from limited reference data, e.g., cross-section SEM images, which are critical to prevent overfitting of the DL model and improve the accuracy of the analysis. The realistic simulations are generated automatically using the NanoDiffract for XCD (NDX) software. The synthetic data are then used to train a convolutional neural network (CNN) that can be deployed and used for real-time inference. We demonstrate this approach by evaluating single-shot alignment and tilt of HAR memory hole structures. The CNN was validated with experimental data collected and analyzed using a Sirius-XCD® tool. Validation with reference data from production quality wafers resulted in an R² > 0.95 and precision 3σ < 0.02 degree with a significant reduction in measurement time per site.

In this work, an AFM platform that could meet the throughput requirements for inline measurement is demonstrated by MEMS AFM devices capable of 3 degrees of freedom (XYZ) movement and is self-sensing. Each MEMS AFM device occupies a footprint of 1 mm² and is mass-manufactured using a scalable CMOS-MEMS process. Furthermore, these MEMS AFMs are low mass and overcome the fundamental speed limitations of traditional bulk piezoelectric scanners. Two relevant applications for semiconductor metrology and inspection are explored using MEMS AFM devices on IPneutral AMAG7 193i test structures. Two specific examples of applications of after etch inspection — line edge roughness metrology and rapid defect inspection — were demonstrated. An array of four simultaneously scanning parallel AFMs is also presented, and topography data collected from a nanoimprinted polymer is shown. The CMOS-MEMS manufacturing process enables the possibility of scaling AFMs to achieve simultaneous scanning of thousands of sites. The massive parallelization of AFMs enables true wafer map sampling and paves the path toward parts per billion defect control and massive metrology with high wafer coverage.

Fab metrology and defect inspection workflows have reached an inflection point with the introduction of gate-all-around (GAA) and high aspect ratio memory structures. Few existing inspection and metrology tools can match the sub-surface imaging and analytical capability provided by (Scanning) Transmission Electron Microscopy ((S)TEM). Fully automated (S)TEM workflows are becoming a necessity for the industry to deliver high volume metrology reference data. This atomic scale data must be available with fast turnaround and must also be statistically valid to speed up learning cycles. In this study, we present (S)TEM metrology characterization of advanced GAA and 3D NAND devices by an automated MetriosTM TEM. We introduce an internal machine learning-based modeling algorithm to address the challenges of recognizing GAA devices with process variations and provide faster access to highly accurate TEM reference metrology data. We present automated EDS characterization of beam-sensitive ONO layers, which is a key challenge in 3D NAND device metrology, enabled by a new generation of EDS detector with a high collection efficiency. We also present results on (S)TEM metrology during process monitoring of GAA devices with a higher level of TEM automation.

A diffraction-based measurement of overlay requires a target composed of two cells per direction of measurement, with induced shifts of opposite signs designed into each of the cells. We present a method for a measurement which only requires a single cell per direction. This is achieved by resolving the image in the pupil plane and using the angle of incidence inlieu of the induced shift. The use of single-celled targets reduces the target size by half and enables the placement of the target in-die, as well as reducing the measurement time. This single-cell measurement requires the calibration of the target’s optical stack height, which is done on a small number of two-cell targets. This calibration also produces a stable map of the aligned layers’ height profile across the wafer.

Optical constants of materials are essential for predicting and interpreting optical responses, which is crucial when designing new optical components. Although accurate databases of optical constants are available for some regions of the electromagnetic spectrum, for the vacuum ultraviolet (VUV), the extreme ultraviolet (EUV), and soft x-ray spectral ranges, the available optical data suffer inconsistencies, and their determination is particularly challenging. Here, we present a selected example of ruthenium (Ru) for the determination of optical constants from the VUV to the soft x-ray spectral range using reflectivity measurements performed with synchrotron radiation. The subtleties of reflectivity measurements are discussed for a large wavelength range, from 0.7 to 200 nanometers.

For advanced nodes, a robust metrology is required to estimate EPE and its contributors. Especially when moving to late process development steps (Ramp-Up and High Volume Manufacturing (HVM)) where inter and intra wafer variations are small but crucial. In this study, we used 8um by 8um SEM images to assess the benefit of large Field-of-View (LFOV) metrology. The result proves the capability of LFOV metrology in capturing not only intra-wafer EPE behavior and its sensitivity to minor variations but also the minor wafer-to-wafer (W2W) variations which is not possible using a small FOV (SFOV) metrology (0.5um by 0.5um) due to larger noise level.

3D heterogeneous integration is an evolving segment in integrated circuit development and advanced packaging to drive More than Moore (MtM) chip scaling. Heterogeneous integration allows IC manufacturers to stack and integrate more silicon devices in a single package, increasing the transistor density and product performance. Product designers seek to gain higher bandwidth, increased power, improved signal integrity, more flexible designs (mix/match different chip functions, sizes, and technology nodes), and lower overall costs. The 3D heterogeneous integration roadmap strives to reduce the bonding bumps/pads pitch to a sub-micrometer level, enabling a higher bump I/O density. Key process development activity is occurring in the wafer-to-wafer (W2W) bonding process to reduce interconnect pitch to 10μm and below. In the W2W process, a wafer bonder is used to align and bond two whole wafers. The bonded wafers are then cut up into stacked chips using a dicing process and undergo testing and further packaging. To successfully unite these two bond surfaces with a very small pitch, tight control of the bond pad alignment is required to make sure the copper pads to be bonded line up perfectly, driving an increased need for overlay metrology precision and die-bonder control. Overlay metrology challenges include thick silicon and tight overlay (OVL) error specifications to enable tight and fast on-product overlay (OPO) control for 3D NAND product development. This work will evaluate the various aspects impacting OPO, including the pre and post-bonding error budget, accuracy, measurability, robustness, and throughput.

With the extreme ultraviolet (EUV) lithography and its pitch scaling, the resist shrinkage from electron beam has returned to an important critical dimension (CD) control issue—unlike multi-patterning where the smallest CD is larger than 40nm. The resist height reduces to maintain the aspect ratio below 2:1 which is critical factor for the prevention of the resist collapse. This leads to huge challenges to minimize the shrinkage of resist during the scanning electron microscope (SEM) measurement. Accurate and precise metrology of chemically amplified resist (CAR) type EUV photoresist processed pattern utilizing classical beam energy for lithography pattern such as 500V is great challenging as electron beam exposure of 1^st measurement already fully shrunk the pattern. Moreover, occurrence of carbonization along with shrinkage hinders finding best conditions for not only metrology optimization but also minimized process impact. In this work, we evaluated the magnitude of shrinkage of CAR type EUV photoresists with several approaches including 0_th and 1^st shrinkage estimation utilizing line & space pattern and contact hole pattern as a function of landing energy dose and static/dynamic repeatability method to distinguish behaviors of shrinkage and carbonization by controlling interaction time of photoresist to its environment. One approach to trace minimized 0^th shrinkage and metrology uncertainty in lithography process is utilizing 1^st shrinkage (1^st CD – 2^nd CD) analysis together with plotting absolute value of the 1st CD as a function of dose. The other approach to trace optimization condition was comparing exposed area with electron beam and non-exposed area achieved by comparing litho/etch consecutive process on the same area. Furthermore, model fits, a simulation study were also performed.

Accompanying the micro-fabrication and the complexity of the semiconductor manufacturing process, measurement and inspection using a scanning electron microscope (SEM) have become increasingly important for semiconductor manufacturing. To photograph high signa-to-noise ratio (SNR) images for precise measurement and precise inspection, conventional methods must reduce the noise by accumulating multiple low SNR images irradiated by an electron beam at the same point multiple times. However, such multiple irradiations increase sample damage and measurement and inspection turnaround time. To accelerate the turnaround time and improve performance of measurement and inspection using advanced image processing, we evaluated deep learning-based denoising algorithms that show significant denoising performance compared to the conventional method. Both supervised and self-supervised learning are mainstream deep learning denoising algorithms. The former requires advance preparation of high SNR images, unlike the latter. However, SEM can acquire higher SNR images by averaging more frames. In addition, the cost of acquisition of the training images can be ignored in the fabrication process when the number of training image sets is small. Therefore, in this study, we trained several supervised and self-supervised learning methods on a small dataset comprising hundreds of images and compared their results. The denoising performance for low SNR SEM images of semiconductor circuits was compared using peak signal-to-noise ratio (PSNR), similarity index measure (SSIM), image contrast, and critical distance (CD) values. The results showed that supervised learning achieved higher performance. In addition, we propose a new framework that conducts CD measurements using high SNR images during training and feeds the results back into the model optimization for supervised training. The results showed that the proposed method has potential to improve many metrics.

On product overlay (OPO) is one of the most critical parameters for the continued scaling according to Moore’s law. Without good overlay between the mask and the silicon wafer inside the lithography tool, yield will suffer¹. As the OPO budget shrinks, non-lithography process induced stress causing in-plane distortions (IPD) becomes a more dominant contributor to the shrinking overlay budget². To estimate the process induced in-plane wafer distortion after cucking the wafer onto the scanner board, a high-resolution measurement of the freeform wafer shape of the unclamped wafer with the gravity effect removed is needed. Measuring both intra and inter die wafer distortions, a feed-forward prediction algorithm, as has been published by ASML, minimizes the need for alignment marks on the die and wafer and can be performed at any lithography layer3. Up until now, the semiconductor industry has been using Coherent Gradient Sensing (CGS) interferometry or Fizeau interferometry to generate the wave front phase from the reflecting wafer surface to measure the free form wafer shape^3,4,5. In this paper, we present a new method, Wave Front Phase Imaging (WFPI) for generating a very high-resolution wave front phase map of the light reflected off of the patterned silicon wafer surface. The wafer is held vertically to allow for the free wafer shape to be measured without having the wafer shape be impacted by gravity. We show data using a WFPI patterned wafer geometry tool that acquires 16.3 million data points on a 300mm patterned silicon wafer with 65μm spatial resolution using a total data acquisition time of 14 seconds.

Automotive semiconductor products demand high reliability. The current process of performing electrical test after fab-out may not be sufficient for efficient reliability management. This paper proposes an AI solution for improving the reliability of automotive semiconductor products. The solution includes two unique concepts: fab-data augmentation (FDA) to estimate missing values using partially available measurement data during the fabrication process and real-time prediction of reliability using machine learning (ML) models. The ML model is also used to identify and rank critical process steps that impact reliability, and to predict the reliability of wafers in real time. This allows low reliability wafers to be screened out early during the chip fabrication process, improving the overall reliability of the final product.

Yield prediction is highly beneficial in semiconductor manufacturing and hence has attracted significant research interest. A number of recent techniques to do so have utilized machine-learning techniques to improve prediction accuracy. However, the diversity of algorithms used in the wide application domains of semiconductors fabrication make it difficult to compare them as well as to identify key models to use in future. In this paper, we navigate this diversity by conducting an extensive literature research with the aspects of the different data used and the different algorithms applied. Various ML algorithms have their unique strengths and weaknesses, which makes them differently suited for different aspects of yield prediction. In addition, we also consider whether regression analyses or classification analyses are used to nd potentials and pitfalls in this area. We will analyse the type of data being used and various pre-processing techniques proposed. In addition, we will also analyse the practical implementation of these models. A lot has already been achieved on yield prediction, but every future improvement that enables significant cost saving by making it easier to optimally coordinate the individual processes and perhaps detect errors earlier is more than welcome. This review paper provides a foundation for model and data selection for yield prediction based on current state of the art.

We present a reflective Fourier ptychographic microscopy (FPM) with a deep ultraviolet (DUV) laser and a high numerical aperture objective for sub-100nm imaging of an opaque target used in semiconductor device manufacturing. An aperture scanning illumination system designed for a laser with high energy fluence is implemented for angle-varied illumination. Performance of the DUV FPM is evaluated and compared to conventional DUV microscopy by imaging a series of molybdenum silicide (MoSi) multiline with a minimum linewidth of 80 nm, showing that contrast enhancement ratio increases as the linewidth of the target decreases.

The evolution of 3D NAND memory devices is increasing the depth of HAR (High Aspect Ratio) hole structure. Consequently the technology to measure the shape of the structure is also becoming more difficult. In general, optical measurement method such as OCD (Optical Critical Dimension) is mainly used for measurement of the HAR structure, but optic technology has limitation in measurement of hole structure independently. To overcome this, SEM (Scanning Electron Microscopy) with high acceleration voltage of electron beam can be used for the measurement of bottom CD (Critical Dimension, diameter of a hole) of the hole structure. However this technology also has challenge in that the measured CD does not always represent the exact bottom CD of the structure. In order to solve this problem, we propose a method of inferring the actual depth where the measured CD is located by examining the change of the acceleration voltage and the angle of incident electron beam. The CDs of real product hole pattern were measured according to the change of landing energy of electron beam and the measured depth was calculated using proposed method. After inferring the CD measured from the actual hole structure, the method is verified in a sample having known structure figures. The proposed method can be used for 3D microstructure measurements using SEM technology in the future.

Optimal color weighting (OCW) is a promising technique to improve accuracy and robustness of alignment mark measurement in the lithography process. Measurement based OCW shows remarkable improvement of overlay error under laboratory conditions. In those conditions, one of the wafer processes is split and a simple form of mark deformation is present. However, the OCW effect has not been confirmed in the case of on-product overlay since various of deformations are mixed in the real FAB. We perform simple simulation showing that mixed deformations can deteriorate the performance of OCW and show that utilizing spatial characteristics of the wafer with OCW further improves the overlay error. As a result, we have improved on-product-overlay form 3.78 nm to 3.51 nm or 7.1% using data of 86 lots, 268 wafers in DUV layer of 3 nm logic device.

Total measurement uncertainty (TMU) is a commonly used key performance indicator (KPI) for tool-induced error in metrology systems. Several definitions of TMU are being used today for overlay metrology (OVL), with the leading definition being the root-sum-square (RSS) of three other KPIs: the wafer mean Tool Induces Shift (TIS𝜇), the wafer variability of TIS (TIS3σ), and the OVL measurement reproducibility (OVL precision). A multitude of TIS management methods has been developed and implemented over the years for calibrating out the raw TIS from OVL. With these TIS management methods in place, the use of the raw TISμ and TIS3σ in TMU no longer serves as a good characterization of the total tool-induced error. In this paper, we describe a procedure for evaluating the actual, post-TIS management, OVL Metrology TMU through the introduction of two new wafer level indicators: the effective wafer means TIS (eTISμ), and the effective wafer TIS variability (eTIS3σ).

Nanostructured semiconductors can exhibit thermal properties unachievable in bulk systems and will play a crucial role in next-generation nanoelectronics and energy efficient devices, where heat evacuation poses a critical limitation. However, first principles models are too computationally challenging for 3D nanostructured geometries, while ballistic phonon descriptions make overly-simplistic assumptions about the nature of phonon-boundary interactions. Here, we study heat flow in a 3D nanostructured silicon metalattice of <<100nm feature size, using an infrared pump laser to excite the sample and an extreme ultraviolet probe to monitor its relaxation. Analyzing surface acoustic waves launched by metallic gratings fabricated on the sample surface, we nondestructively extract the metalattice’s elastic properties and porosity, validated by electron tomography, which are required parameters to model the heat flow. With the same measurement, we observe the heat flow dynamics to exhibit a Fourier-like behavior with an ultra-low apparent thermal conductivity. Through an analogy to rarefied gas flow in porous media, we explain this and similar measurements of phonon transport in silicon nanomeshes, porous nanowires and nanowire networks. We separate the geometry-dependent permeability contribution to thermal conduction from an intrinsic viscous component, which scales universally with porosity across all systems where feature sizes are much smaller than the dominant phonon mean free paths. This leads to an analytic description of thermal conduction in highly-confined silicon nanosystems, enabling their representation as effective media in engineering applications.

Publisher's Note: This paper, originally published on 27 April 2023, was replaced with a corrected/revised version on 31 July 2023. If you downloaded the original PDF but are unable to access the revision, please contact SPIE Digital Library Customer Service for assistance.