14 nm FinFET low-power single port SRAM with power-gating and multi-VDD

Zhongda Zhang; Yuling Yan; Lijun Zhang; Yuan Lou

doi:10.1117/12.2671271

29 March 2023 14 nm FinFET low-power single port SRAM with power-gating and multi-VDD

Zhongda Zhang, Yuling Yan, Lijun Zhang, Yuan Lou

Proceedings Volume 12594, Second International Conference on Electronic Information Engineering and Computer Communication (EIECC 2022); 1259406 (2023) https://doi.org/10.1117/12.2671271
Event: Second International Conference on Electronic Information Engineering and Computer Communication (EIECC 2022), 2022, Xi'an, China

Abstract

SRAM occupies the main area of SoC, its power consumption performance become crucial. Low power SRAM is widely used in IOT device. Power-gating circuit can help SRAM hold low static power during non-read/write period, and multi-VDD using different voltage thresholds in different modules can help SRAM acquire low dynamic power. Read-Write assistant circuit composed by NMOS capacitor helps SRAM read and write faster than before to gain a fast timing performance, and it helps SRAM get the feature of low Vmin and DRV. This design in single port SRAM was tape-out by 14nm FinFET process, and it was verified by ADVANTEST V93000 test platform. The all test result of Vmin, current and data retention voltage meet the single port SRAM design requirements.

Citation Download Citation

Zhongda Zhang, Yuling Yan, Lijun Zhang, and Yuan Lou "14 nm FinFET low-power single port SRAM with power-gating and multi-VDD", Proc. SPIE 12594, Second International Conference on Electronic Information Engineering and Computer Communication (EIECC 2022), 1259406 (29 March 2023); https://doi.org/10.1117/12.2671271

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