Design of image parallel compression system based on FPGA

Chaoqun Ma; Zhiyong Xu; Yao Zhang

doi:10.1117/12.2681349

8 June 2023 Design of image parallel compression system based on FPGA

Chaoqun Ma, Zhiyong Xu, Yao Zhang

Proceedings Volume 12707, International Conference on Image, Signal Processing, and Pattern Recognition (ISPP 2023); 1270705 (2023) https://doi.org/10.1117/12.2681349
Event: International Conference on Image, Signal Processing, and Pattern Recognition (ISPP 2023), 2023, Changsha, China

Abstract

In order to solve the problem of high-speed image compression, this paper designs a parallel bit-plane encoding algorithm based on CCSDS image compression algorithm, and uses FPGA to implement it. Experimental results show that the system can effectively reduce the image coding time and meet the requirements of high-speed image compression.

Citation Download Citation

Chaoqun Ma, Zhiyong Xu, and Yao Zhang "Design of image parallel compression system based on FPGA", Proc. SPIE 12707, International Conference on Image, Signal Processing, and Pattern Recognition (ISPP 2023), 1270705 (8 June 2023); https://doi.org/10.1117/12.2681349

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available