An error verification design of DDC based on MATLAB and FPGA

Rendi Deng; Rui Tang

doi:10.1117/12.3006208

10 October 2023 An error verification design of DDC based on MATLAB and FPGA

Rendi Deng, Rui Tang

Author Affiliations +

Proceedings Volume 12799, Third International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023); 1279909 (2023) https://doi.org/10.1117/12.3006208
Event: 3rd International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023), 2023, Kuala Lumpur, Malaysia

Abstract

The main work of this paper is to study the error verification problem of radar echo signal DDC algorithm implementation, and DDC has certain innovations in hardware implementation methods. The main design modules of DDC include band-pass filtering, mixing, low-pass filtering, decimation and zeroing. In the design and verification of DDC system, the time-domain dual-frequency chirp echo signal is first simulated, and the DDC processing process is verified by advanced floating-point simulation on the MATLAB platform to verify its feasibility and correctness. Then, through Verilog HDL programming, the FPGA-based DDC implementation is carried out, and the output results of each module are simulated through Medelsim. Finally, the simulation results in each FPGA module are calculated with the simulation results in MATLAB to verify the accuracy of the hardware design.

(2023) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Rendi Deng and Rui Tang "An error verification design of DDC based on MATLAB and FPGA", Proc. SPIE 12799, Third International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023), 1279909 (10 October 2023); https://doi.org/10.1117/12.3006208

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