This PDF file contains the front matter associated with SPIE Proceedings Volume 12802, including the Title Page, Copyright information, Table of Contents, and Conference Committee information.

With already more than 160 EUV scanners operational worldwide, the promise of EUV lithography became a high-volume-manufacturing reality in the past few years. Moreover, EUV lithography has now become the main enabler for the latest generations of chips we all know and use. ZEISS and ASML keep on developing the capability of EUV tools to further enable upcoming generations of chips. The next step is an increase of the numerical aperture (NA) of our optics from currently 0.33 to 0.55. These high-NA tools will support the shrink prescribed by Moore's Law to continue well into the next decade, by allowing lithographers to print 8nm half-pitch in a single exposure. We will give an update on the current production status at ZEISS: not only on mirror surface polishing, coating, metrology, but also on mirror handling and integration. Moreover, we will also present the current status and prospects of 0.33-NA optics.

This paper focuses on the design and fabrication of phase-shifting transmission masks tailored for high-resolution nanopatterning using a compact EUV exposure tool. The authors analyze various factors that influence the achievable resolution, aiming to push the boundaries towards the sub-10 nm range, approaching the theoretical resolution limit. The demand for high-resolution nanoscale patterns spans across diverse applications, driving the need for compact exposure tools and lithographic concepts. The developed EUV exposure tool can be operated at either 10.9 nm or 13.5 nm exposure wavelengths depending on the specific use case. This capability allows for large area nanopatterning with enhanced throughput as well as industrial resist qualification with focus on highest resolution. The utilized discharge-produced plasma (DPP) EUV source offers partially coherent radiation. For this radiation type, the (achromatic) Talbot lithography has proven to be the most effective with resolution in the sub-30 nm range and a theoretical resolution limit of less than 10 nm. To optimize the intensity distribution in the wafer plane, the authors use rigorous coupled-wave analysis (RCWA) simulations to fine-tune the material composition and geometry of the masks. Various factors influencing the achievable resolution are identified and presented. In addition to simulative optimization, the fabrication of dense periodic nanopatterns poses increasing challenges for smaller periods. In this work, the mask fabrication process is optimized to produce stable and high-resolution periodic mask patterns, leading to record resolutions for both line and contact hole periodic nanopatterns with the presented setup.

Multi-Beam Mask Writers (MBMW) from IMS Nanofabrication disrupted the mask writing technology in the past decade by offering this technology to the industry with a range of benefits over the preceding variable shaped beam (VSB) technology. The MBMW-101 enabled write times independent of pattern complexity, usage of low sensitivity resists at high throughput, and providing superior resolution and critical dimension uniformity (CDU) capabilities. With these benefits, the technology enabled high volume extreme ultra violet (EUV) mask manufacturing for logic and memory applications to the industry. The MBMW-201 is today’s standard technology for leading edge photo masks patterning and used in the most advanced mask shops around the globe. Its superior robustness and powerful write modes allow an unprecedented writing efficiency and resolution capability. Now IMS broadens the spectrum of application for this technology and releases two new products: The MBMW-100 Flex is a versatile mask writer to open multi-beam benefits to mature and intermediate nodes application at high throughput and beneficial total cost of ownership, targeting nodes from 32nm down to 10nm. The MBMW-301: the next generation leading edge mask writer for ultra-low sensitivity resists with resolution and CDU capabilities meeting EUV high numerical aperture (NA) requirements targeting nodes down to 2nm and beyond. This article will delve into the transformational journey of multi-beam mask writing, from its early beginnings to its current status as the cornerstone of EUV mask production and provide an overview on the two new models with performance data and lithography results.

An automated system has been developed to calculate dose and bias XY, based on the relevant characteristics of the single mask layout, material parameters, general process inputs from the production SPC and equipment-related input, such as the QC test masks.. Mask input parameters are Exposure Bias, feature size, local exposure ratio (1500μm x 1500μm square), micro exposure ratio (25μm x 25μm square) and coordinates of its CD measurement points. Feature size is used to centre the writing process based on CD linearity. The exposure ratio is used to correct over/under exposure related to process loading effects. Micro exposure ratio (MER) is also used to find the best exposure condition to minimize the effects of Iso-Dense bias. To calculate the exposure Dose, the global expected CD Error (CDE) is fed to the CDE vs. dose curve, obtained from QC test masks for different feature types (Hole, Iso Line, Iso Space, Dense Line&Space). Exposure Biases are set to work around iso-focal dose or for other needs. The calculated dose is used to determine the correction for X/Y bias, which depends on the dose itself. Based on the model we developed an automated system (called ADOC – ALTA Dose Calculation) which automatically calculates writing parameters and sets the job request directly on the writing tool. Thanks to this system we increased writing parameters’ reliability and obtained a CD yield close to 100%. This system greatly simplifies the activity of writing operators, with fewer manual inputs: the writing step requires only blank loading and running ADOC by simply providing the unique mask code identification. In this paper, we discuss the writing parameters definition model, the application software and its interface with the production line’s database and with the i-line writing tool. We conclude with the achievements we got in terms of yield and process robustness.

Pattern collapse has become a problem area in lithographic manufacturing due to the added complexity as we move towards extreme ultraviolet (EUV) focused mass production of semiconductor devices. Collapse is influenced mainly by the geometry and mechanical properties of the pattern. Photoresist patterns with higher aspect ratios (ARs) or lower feature spacing (dense features) are prone to collapse. This, combined with a lower stiffness value (Young’s modulus), adds to the undesirable deformation of patterns at the wafer level as we move towards advanced technology nodes. Such a deformation in the resist is seen after the rinsing stage and is caused mainly due to the non-uniform drying of the rinse liquid after chemical development. The main causes of this are the unbalanced Laplace pressure ΔP difference across the liquid-air interface and the surface tension force (STF) along the three-phase line. In addition to that, the sidewall surface roughness leads to localized regions of higher aspect ratios which makes collapse modeling in EUV lithography more challenging. The irregular variation in the aspect ratios increases the risk of collapse and also requires additional model considerations. A machine learning (ML) based approach is introduced to predict deformation characteristics for rough cross-sections (XZ plane) which is then utilized for the computation of the overall deformation of an entire lines and spaces (L/S) pattern. The 3D profiles are converted into a 2D representation using modified Fisher vectors (FVs) and labeled based on the estimated deformation of the given rough profile. A convolutional neural network (CNN) is then trained with the data generated and used to predict collapse probabilities for a given data set. For the prediction of collapse in pillar patterns, a slightly different ML-based approach is used based on the cross sections in the XY plane. A finite element method (FEM) model is implemented to calculate the deformations δ for a given pillar arrangement which then serve as labels for the training data. The cross-sections are stacked together along the height/thickness and a 3D convolutional neural network is trained and used for collapse prediction.

Background: Well-designed test patterns are required to ensure a robust patterning involving mask, lithography and etch. They are expected to anticipate potential process challenges while representing well the layout diversity. Problem: We expect good test patterns to have a high design space coverage with minimal redundancy. Is it possible to get optimal design contents while keeping a small footprint and following the design rules? Approach: In this work, after defining specific optical and geometrical features and discretizing the pattern as a binary matrix, we propose to use the signature of the pattern in the feature space to assign a score measuring the usefulness of the pattern. The score is used as a cost function to drive an iterative optimization of the pattern shape based on a differential evolution algorithm. Conclusion: We demonstrated how to generate compact test patterns with high design diversity customized to specific applications that should help to anticipate, represent or monitor well process challenges.

Flow from circuit design to manufacturing a mask is a complex process. A mask is used to print a particular design feature. Extraction of accurate CD contour geometries from ADI (after developed inspection) SEM images plays a pivotal role for a qualitative lithographic process as well as to verify device characterization in aggressive pitches. In our previous work, it has been shown how deep learning based de-noising is helping to improve the contour detection accuracy. We analysed and validated our result with noisy/denoised image pair for categorically different geometrical patterns, such as, L/S (linespace), T2T (tip-to-tip), pillars with different scan types etc., by using a programmable tool (Calibre®SEMSuite^TM) for contour extraction and further analysis metrics. The comparative analysis demonstrated that denoised images have significantly higher confidence analysis metrics, reduced number of missing patterns as well as false bridges against raw noisy images while keeping the same parameter settings for both data inputs. We have demonstrated that our proposed method is capable to extract contours on the body of the noisy SEM images with accuracy in close proximity with design data. By combining these advanced algorithms as options in Calibre®SEMSuite^TM, users would be able to process large amount of information for data cleaning, classification & further model calibration intelligently.

Background: Stochastic effects are manifested by local variabilities in critical dimension (CD), shape, size and placement of patterns. On previous works, a commercial software has been used to extract contours from CDSEM images, from which various metrics are computed to quantify these variabilities. Last year, an image processing system has been implemented to monitor these indicators in a high-volume manufacturing (HVM) environment. This system automatically extracts these contour-based metrics from the in-line images. Aim: The study has been divided into two parts. The first objective was to show the ability to detect a mismatch between two lithography clusters, not revealed by traditional CD in-line trends. Since investigations identified that this mismatch was caused by differences in the rinse recipes, the second objective was to gain a deeper understanding of the impact of rinse on both metrology and patterning. Approach: In addition to the traditional CD measurements, the following metrics are also monitored: Local CD Uniformity (LCDU), Pattern CD Uniformity (PCDU) and Centroid Shift Uniformity (CSU). Results: Baselines for the 28 nm contact process have been established, providing new indicators to compare and monitor processes and tools in the fab. PCDU computed on post-lithography images proved to be an effective detector of clusters mismatching, not identified by the CD criterion. Upon investigation, engineers discovered differences in the rinse recipes between the two lithography tools. To analyze the influence of rinse, an R&D experiment was conducted, repeating this very same step 2, 4 and 6 times in a row. As rinse steps number increased, two observations have been made: SEM images are more distorted, and the shape variability indicator (PCDU) increases. The most likely explanation is that increased friction with the deionized water during the rinse results in more stored electrical charges at the wafer surface, which affects the resist (increased “roughness”) and disturbs the SEM image acquisition. Conclusions: By implementing a remote metrology system to perform extensive analysis of in-line CD-SEM images with a contour extraction software, a cluster mismatching (not from the CD point of view) was identified in a HVM environment. This enhanced in-line monitoring enabled us to find the parameter to be adjusted to match them, thereby avoiding any adverse effects. Experiments confirmed that rinse negatively affects both SEM image fidelity (increased distortion) and process uniformity (decreased shape uniformity).

With the machine learning breakthroughs in the past few years, the number of studies applying this principle to lithography steps is increasing constantly. In this article, the focus does not concern the learning models for OPC masks improvement, but the optimization of the data used for such learning. This part is essential for a good learning process, but has rarely been studied, despite its impact on the output results quality being as important as an improvement of the learning model. Several optimization methods are discussed, each with a specific objective: either reducing learning time, increasing the obtained results quality, or both. To evaluate these different results, classical optical proximity correction simulation tools are used, allowing for a complete evaluation in line with production standards.

The concept of dual layer pattering as an alternative to POR in interconnect formation has been evaluated on maskless exposure technology. The novel dielectric materials negative tone PBO were used for the concept prove. The process optimization was conducted by varying the exposure and spin coating paraments. The lowest feature size accomplished was even <4 μm proving the two–step structures with FT of the first layer 50% of the dual layer FT. This new concept represents contribution to the improved CoO setup in the advanced packaging processes.

On product overlay (OPO) is one of the most critical parameters for the continued scaling according to Moore’s law. Without good overlay between the mask and the silicon wafer inside the lithography tool, yield will suffer. As the OPO budget shrinks, non-lithography process induced stress causing in-plane distortions (IPD) becomes a more dominant contributor to the shrinking overlay budget. To estimate the process induced in-plane wafer distortion after cucking the wafer onto the scanner board, a high-resolution measurement of the freeform wafer shape of the unclamped wafer, with the gravity effect removed, is needed. A high-resolution wafer shape map using a feed-forward prediction algorithm, as has been published by ASML, can account for both intra and inter die wafer distortions, minimizing the need for alignment marks on the die and wafer in addition to that it can be performed at any lithography layer. Up until now, the semiconductor industry has been using Coherent Gradient Sensing (CGS) interferometry or Fizeau interferometry to generate the wave front phase from the reflecting wafer surface to measure the free form wafer shape. However, these techniques have only been available for 300mm wafers. In this paper we introduce Wave Front Phase Imaging (WFPI), a new technique that can measure the free form wafer shape of a patterned silicon wafer using only the intensity of the reflected light. In the WFPI system, the wafer is held vertically to avoid the effects of gravity during measurements. The wave front phase is then measured by acquiring only the 2-dimensional intensity distribution of the reflected non-coherent light at two or more distances along the optical path using a standard, low noise, CMOS sensor. This method allows for very high data acquisition speed, equal to the camera’s shutter time, and a high number of data points with the same number of pixels as available in the digital imaging sensor. In the measurements presented in this paper, we acquired 7.3 million data points on a full 200mm patterned silicon wafer with a lateral resolution of 65μm. The same system presented can also acquire data on a 300mm silicon wafer in which case 16.3 million data points with the same 65μm spatial resolution were collected.

We have developed novel Design Based Metrology (DBM) technology which enables metrology engineers to utilize not only 2-dimensional metrology with high precision but also high number CPU cores to reduce calculation time. It is crucial to maximize efficiency of parallel processing with high number of CPU cores and reduce overhead. We designed new DBM software based on the concepts of our novel DBM technology and build the DBM PC Cluster system consisting of the software and the latest computer system which meets the concept. The DBM PC Cluster system processing performance shows greater than several thousand images per hour capacity. In this paper, we will report the evaluation results and scalability for future mask metrology.

In this paper the development of an intra-level mix and match (ILM&M) process, an expression for the exposure of one resist layer with at least two different exposure technologies, for the negative tone resist mr-EBL 6000.5 (micro resist technology, Germany) is demonstrated. Process development is conducted on a layout with photonic integrated circuit (PIC) related waveguides (WG), ring resonators and coupling structures on 150 mm silicon wafers with a 1000 nm SiO₂ layer and a 450 nm low pressure (LP) Si₃N₄ layer on top. In order to match the intended structure dimensions perfectly, the ideal exposure dose has to be determined with an i-line wafer stepper and in parallel with an e-beam lithography (EBL) system. In addition, different post exposure bake (PEB) processes and their influence on resulting structures, which are investigated by means of CD-SEM and profilometer measurements are investigated. It is shown, that regarding pattern fidelity, coupling structures exposed by EBL match the layout design better than those exposed by the i-line stepper. For the purpose of further optimizing the matching of generated coupling structures to the targeted design, different proximity effect correction (PEC) parameter sets are applied. CD-SEM measurements reveal the PEC parameter set which is most suitable for generating the targeted coupling structures. By combining the measurement results of structures exposed with different exposure doses and selecting the best PEC parameter set regarding structure dimensions and pattern fidelity, a processing recipe for an e-beam/i-line stepper ILM&M with the negative tone resist mr-EBL 6000.5 is successfully established.

Universal quantum computers promise the possibility of solving certain computational problems significantly faster than classically possible. For relevant problems, millions of qubits are needed, which is only feasible with industrial production methods. This study presents an electron beam patterning process of gate electrodes for Si/SiGe electron spin qubits, which is compatible with modern CMOS semiconductor manufacturing. Using a pCAR e-beam resist, a process window is determined in which structure sizes of 50 nm line and 30 nm space can be reproducibly fabricated with reasonable throughput. Based on electrostatic simulations, we implemented a feedback loop to investigate the functionality of the gate electrode geometry under fabrication-induced variations.

The development of EUV scatterometry, as a potentially interesting option for the characterization of photomasks, has made significant progress in the last decade. The at-wavelength performance is directly assessed, and the measurements are potentially fast, a relevant precondition for the development of production-worthy instruments. However, an accurate prediction of the imaging properties requires a high effort in simulation and the precise determination of fundamental parameters such as the optical constants to correctly model the interaction of the EUV radiation with the nano-structured EUV mask. Another possibility to further increase the sensitivity and minimize the uncertainties in the reconstruction could be a polarization-resolved analysis of the scattered EUV radiation. The high degree of linear polarization of the beamline is ideal for investigating this question. However, it remains to be proven whether the additional measurement effort leads to a reduction of the uncertainties in the geometric reconstruction of the nanostructures. Besides theoretical modeling addressing this question, we also present benchmark measurements performed by PTB at the soft X-ray beamline of BESSY II.

The paradigm switch to a reflective mask design for EUV lithography has proven to be challenging. Within the Horizon2020 PIn3S program Zeiss and imec are collaborating to address some of these challenges. In this work, an EUV mask with a collection of programmed defects representative for the 3nm technology node was reviewed. Defect printability at wafer level was analyzed after exposure on the ASML NXE:3400B by SEM. Furthermore, the mask was analyzed on the Zeiss AIMS® EUV platform and by SEM. For P36 (1x) 1:1 L/S programmed extrusions we have demonstrated that AIMS® EUV can be used to predict ADI local defect widths as well as (μ)bridge printability. Moreover, from P36 to P32 the mask spec regarding allowed opaque L/S extrusion widths needs to be tighter considering an earlier onset of ADI (μ)bridge printability and a stronger than expected ADI defect width increase through pitch.

The Advanced Mask Technology Center (AMTC) is a joint venture of GlobalFoundries and Toppan Photomasks. AMTC delivers supreme quality photo masks for an enormous variety of different products. To compete with the constantly increasing quality requirements, data pre-processing becomes more and more a key component to reach required yield performances. To reach the quality requirements for the critical dimension (CD) of our masks we predict correction maps in order to improve CD uniformity and a process bias to improve CD mean to nominal (MTN). The process bias is defined as the difference of written structure size to the final structure dimensions on the completed mask. In this talk we present our path to our first machine learning based process bias model with an overall improvement of CD mean to nominal capability of around 30%. We take a closer look on model performance depending on the general model and feature design.

Wafer CD Uniformity (CDU) and pattern fidelity are useful properties to monitor when considering yield improvement and scaling to smaller dimensions. Besides control of process fluctuations (e.g., focus, dose), wafer stack film thickness uniformity, and image quality (e.g., contrast), quality of mask manufacturing and OPC models are essential to optimize these properties. Therefore, a proper characterization of the written mask dimensions is becoming more and more important, especially as the mask pattern complexity increases through Inverse Lithography Technology (ILT) as well as the need for curvilinear or all-angle designs. Applying contour-based mask quality assessment instead of traditional gauge-based characterization of mask dimensions allows to intrinsically capture mask imperfections like corner rounding (CR) of the absorber for complex shapes which would be hard to measure and categorize by using only a few gauges. Thus, in our study, we examine ways to use contour-based mask characterization methods, including CD and area uniformity, linearity, and CR determination to evaluate mask quality. We present a method and flow to automatically extract contours and determine values for mask CR from top-down mask SEM images. Contour-based metrology and data evaluation is then used to quantitatively address the above-mentioned mask properties of interest. Finally, as an initial approach to investigate impact of mask quality on wafer printing, we apply a generic EUV model to ideal and imperfect masks and compare the simulated contour results. Using realistic mask patterns for lithography modeling and simulation is considered essential to achieve the required accuracy for advanced nodes and technologies.

Background: In the semiconductor industry, CD-SEM (Critical Dimension Scanning Electron Microscope) are key metrology tools used in the control of integrated circuit manufacturing processes. In recent years, several approaches have been evaluated to better monitor these measurement tools from the images generated. One of the promising methodologies is the image sharpness score calculated from the grey levels present on an image. The industrialization of this metric is a major and essential challenge in the CD-SEM image quality monitoring improvement, particularly in the detection of blurred images that can cause erroneous CD (Critical Dimension) measurements. However, the implementation of such an indicator can be complex due to the number of different tool generations and the different beam conditions that can co-exist within the same factory. The diversity of technologies, patterns type, layers and materials add an additional constraint to its industrialization. Aim: This study presents the work done from sharpness score extracted from CD-SEM images to industrialize this score as a metrology indicator. It is based on analyses performed in a production environment comprising a diversity of 4 CD-SEM generations (18 tools) and various products. The objective is to define grouping rules allowing the industrialization of this metric with the aim of detecting equipment drift while offering a better piloting of the metrology equipment capabilities. The interest in this automation will also be to improve out-of-control events treatment efficiency, which are today dependent on human appreciation of image quality. Approach: To systematically save the images and calculate the image sharpness score in real time, a database system was used, coupled with a Virtual Machine (VM) on which software from Aselta Nanographics was installed. The IQ (Image Quality) module of this software was used in this study capable of providing a score on any CD-SEM image without the need to perform any edge detection or pre-calibration. This Image Lab computing infrastructure has enabled the extraction of image sharpness score from over 35 million CD-SEM images collected in addition to the CD measurements already provided by the measurement equipment. Results: The industrialization of the sharpness score required the evaluation and study of the different parameters that could influence this metric. An overview of these results is presented showing a dependence of the image sharpness score on the different pixel sizes that can be used in CDSEM recipes. The use of different materials can also lead to additional sensitivity and variability which may be different depending on the type of CD-SEM used. Further results will be given to better understand the behavior of the sharpness score and to highlight situations that could not be detected in time currently. Conclusion: The analysis of the image sharpness scores revealed the complexity of industrializing this metric and the need to create smart groupings by context such as pattern type, pattern density, material/process type, pixel size and measurement conditions. Adjusting the right sensitivity to the detection of the sharpness score also appeared to be one of the other key criteria in its industrialization. The evaluation of the contour-based sharpness score could provide an answer in the ease of grouping certain contexts.

During the last decade, the introduction of EUV lithography in high-volume chip manufacturing has been accompanied by the development of technological prerequisites for a future support of the node scaling roadmap. As core element, the next generation EUV scanner with an increased NA of 0.55 will be implemented into wafer fabs within the upcoming few years. In addition to its enhanced resolution, the High-NA exposure tool improves image contrast, and consequently reduces local CDU and defect printing on wafer. To take full advantage of this next leap in lithography, the whole infrastructure including EUV photomask technologies and metrology must keep pace with the scanner progress. In this context, actinic EUV mask measurement represents a unique and variously usable way for the qualification of the mask printing performance under scanner-equivalent conditions. The aerial image metrology is targeted to match the corresponding scanner aerial image by means of the emulation of imaging-relevant scanner properties including wavelength, mask-side NA, through-slit chief ray angle, illumination schemes, and aberration level. To qualify High-NA masks of the anamorphic scanner, a methodology was developed that allows the simultaneous measurement of both NA=0.33 and NA=0.55 reticles based on one isomorphic optical projection optics design. Here, we describe the challenges and corresponding solutions combined with two intrinsically diverse emulation types, NA=0.33 isomorphic and NA=0.55 anamorphic, in one single metrology. Special attention is paid to the emulation of the elliptical scanner NA at reticle, the contrast impact due to vector-effects in High-NA scanner imaging, wafer defocus of an anamorphic system for focus-dose process window determination, the pupil obscuration of the High-NA scanner projection optics, and the scanner facetted illumination by means of physical free-form blades, and by a completely digital solution.

Continual shrinking of pattern dimensions in the semiconductor domain is making it increasingly difficult to inspect defects due to factors such as the presence of stochastic noise and the dynamic behavior of defect patterns and types. Conventional rule-based methods and non-parametric supervised machine learning algorithms like k-nearest neighbors (kNN) mostly fail at the requirements of semiconductor defect inspection at these advanced nodes. Deep Learning (DL)-based methods have gained popularity in the semiconductor defect inspection domain because they have been proven robust towards these challenging scenarios. In this research work, we have presented an automated DL-based approach for efficient localization and classification of defects in SEM images. We have proposed SEMI-CenterNet (SEMI-CN), a customized CN architecture trained on Scanning Electron Microscope (SEM) images of semiconductor wafer defects. The use of the proposed CN approach allows improved computational efficiency compared to previously studied DL models. SEMI-CN gets trained to output the center, class, size, and offset of a defect instance. This is different from the approach of most object detection models that use anchors for bounding box prediction. Previous methods predict redundant bounding boxes, most of which are discarded in postprocessing. CN mitigates this by only predicting boxes for likely defect center points. We train SEMI-CN on two datasets and benchmark two ResNet backbones for the framework. Initially, ResNet models pretrained on the COCO dataset undergo training using two datasets separately. Primarily, SEMI-CN shows significant improvement in inference time against previous research works. Finally, transfer learning (using weights of custom SEM dataset) is applied from ADI dataset to AEI dataset and vice-versa, which reduces the required training time for both backbones to reach the best mAP against conventional training method (using COCO dataset pretrained weights).

Scanning Electron Microscopy (SEM) uses surface-emitted Secondary Electrons (SE) to produce grayscale level images. From these SEM images, an observer can mentally represent the topography of the imaged object. Numerical techniques can additionally provide a quantitative assessment of the topography, which is one of the major challenge in the today microelectronics industry for advanced nodes and more-than-moore devices. In this paper, we propose and validate a non-destructive, fast 3D metrology strategy for microscopic object. Various microlens-like 3D structures are patterned on 300 nm wafers by grayscale i-line lithography. The lenses are imaged by a SEM tool with a four-quadrant SE detector, and also measured by Atomic Force Microscopy (AFM) which serves as 3D reference metrology. Both, AFM and SEM data are co-registered and background is removed. An analytical SEM model is used both for SEM detector calibration and parametric reconstruction. First, we observe that this model poorly describes the entire SEM images of the device under test, partly due to electron screening and reemission effects. Secondly, by weighting the image depending on the quadrant orientation, we show that this model can still be used for both calibration and parametric reconstruction. The parametric reconstructions of microlenses with different footprints and heights match well the reference geometries.

Nanoimprint lithography is a large area, high resolution and cost-effective replication technology for micro- and nanostructures. An interesting possibility in the nanoimprint process is the use of materials that remain a functional part of the final component or device. Such an additive approach offers interesting opportunities in terms of novel applications but also cost reduction and could also contribute to sustainability aspects. This paper is aiming at providing a short noncomprehensive overview on the direct patterning of various functional materials by using NIL for optics and life science applications.

Background:In a fast-growing wafer fab environment with multiple technologies in development and production, enabling capabilities to investigate new metrology or process control solutions in production condition is key. One type of data is of interest to us: the images. To better exploit images, and for now CDSEM (Critical Dimension Scanning Election Microscope) images, an image processing sandbox environment has been put in place to enable a real time image process in a “shadow” mode with respect to production. This sandbox is used to validate solutions and propose them for full integration. Aim: Images are produced in large amounts in a wafer fab. They contain a lot of relevant information that can be extracted thanks to diverse types of software, either internally developed or from external suppliers. Simple demonstration of capabilities is often not enough to evidence the return on investment of a solution. The image lab sandbox is an infrastructure able to compute real time the images generated during production and send the results in a database environment which is connected to our data analytic environment. By doing so engineers can generate trends which are emulating control charts. Approach: The sandbox construction has been presented at SPIE 2022 [1] and more details and results are being proposed for publication in JM3 journal. Figure1 describe the main components are image backup infrastructure, ETL (Extract Transform Load) scripts to send image meta data to a database, scripts (trigger and daemon) that are used to launch “on demand” the usage of chosen software based on the image context, a data base system gathering fab measurement meta data and measurement results from software solution being tested, and a data analytic platform which is used to join data from the sand box to the global fab data system and provide data visualization solution. Results: The sandbox is today mainly used to support the deployment of contour-based metrology solutions but is aimed to interface with any other software solution. In 2022, the sandbox has processed more than 30 million images for diverse kinds of purposes. Currently three different software are running all dedicated to CDSEM images. CDSEM image quality monitoring, various contour-based metrology recipes, and more advanced testing like in device overlay or hotspot monitoring shown in this paper. Conclusion: The image Sandbox is now running as a laboratory to evaluate solutions and validate them for production integration. Applications are either for manufacturing control, tool qualification, R&D. Use cases are today multiple and some of them will be presented in this paper.

To achieve the best on product overlay performance, process induced contributors should be understood, quantified, and addressed. Global wafer overlay penalties have been observed since the etch direction is not always perpendicular to the wafer surface especially at the wafer edge due to the etch chamber geometry and plasma parameter settings. Focus ring concept has been used to compensate etch tilt at the edge however it may be challenging to have zero tilt even with a new focus ring. Etch tool setting optimization can be a solution for accurate overlay control at the wafer edge. Going one level deeper and considering the more local etch-induced overlay penalties, we previously showed that for the inner parts of the wafer there is significant field pattern density dependent etch contribution up to 1-nm at each exposure field although the etch tool is not exposure field aware. In this experimental work, etch tool parameters such as power and pressure have been varied and two different reticles with different pattern densities are used to reveal the nature of global and die-level overlay penalties. Pressure and power settings are found to be critical for the wafer edge. The Spin-On-Glass (SOG) anti-reflection coating is shown to be the main contributor for the intra-field etch-induced overlay. We conclude with this work that etch-induced overlay is successfully mitigated at wafer edge and eliminated at intrafield thanks to the understanding on how etch process generates overlay penalties at global and at the die level.

Overlay requirements are becoming more demanding as the semiconductor device design dimensions continue to reduce in size. Thus, it is increasingly crucial to control overlay under tightened specifications to maximize product yield. To meet these requirements, selecting the best overlay model is important to best manage the lithography process with confidence. A well-characterized overlay model is essential in the wafer production process as it becomes the gauge to optimize product yield, reduce rework process costs and shorten cycle time. In this paper, we will introduce the powerful machine-learning method of Cross-Validation (CV) which helps to improve the prediction capability of an overlay model. This method provides a numerical value that can indicate how well the overlay model predicts the misalignment of a new wafer. Our test result shows that the 5th-order model exhibits an overfitting problem, while the 4th-order model shows good performance. We also discuss how we apply the CV to the correction per exposure (CPE) models that are commonly used.

Shrinking pattern dimensions leads to an increased variety of defect types in semiconductor devices. This has spurred innovation in patterning approaches such as Directed Self-Assembly (DSA) for which no traditional, automatic defect inspection software exists. Machine Learning-based SEM image analysis has become an increasingly popular research topic for defect inspection with supervised ML models often showing the best performance. However, little research has been done on obtaining a dataset with high-quality labels for these supervised models. In this work, we propose a method for obtaining coherent and complete labels for a dataset of hexagonal contact hole DSA patterns while requiring minimal quality control effort from a DSA expert. We show that YOLOv8, a state-of-the-art neural network, achieves defect detection precisions of more than 0.9 mAP on our final dataset which best reflects DSA expert defect labeling expectations. We discuss the strengths and limitations of our proposed labeling approach and suggest directions for future work in data-centric ML-based defect inspection.