Transistor profiling for quantitative evaluation of variability in transistor characteristics due to layout dependent effects (LDEs)

Chikaaki Kodama; Mikiyasu Yamaji; Hiroshi Kitahara; Akira Hokazono; Shigeki Nojima; Piyush Pathak; Kimiko Ichikawa; Jac Paul Condella; Michel Cote; Ya-Chieh Lai; Philippe Hurat

doi:10.1117/12.3010201

10 April 2024 Transistor profiling for quantitative evaluation of variability in transistor characteristics due to layout dependent effects (LDEs)

Chikaaki Kodama, Mikiyasu Yamaji, Hiroshi Kitahara, Akira Hokazono, Shigeki Nojima, Piyush Pathak, Kimiko Ichikawa, Jac Paul Condella, Michel Cote, Ya-Chieh Lai, Philippe Hurat

Author Affiliations +

Proceedings Volume 12954, DTCO and Computational Patterning III; 1295403 (2024) https://doi.org/10.1117/12.3010201
Event: SPIE Advanced Lithography + Patterning, 2024, San Jose, California, United States

Abstract

Stress technologies such as stress liners are used to improve the performance of advanced CMOS devices. Due to the contextual situation of a transistor in the physical design layout, unintended stress from neighboring cells can cause variations in the transistor characteristics. This effect is called Layout Dependent Effect (LDE). In this work we propose a fast method to detect outlier transistors due to the LDEs by profiling and sampling them from the VLSI design with millions of transistors and many devices. The proposed method can reduce the TAT for quantitative evaluation of the LDE for design layouts that have not passed the LVS. We also propose a pattern matching based method to search motifs created by encapsulating neighborhood of outlier transistors with large Vth variations. This enables designers to trace such LDE hotspot patterns and thereby outlier transistors during the design phase.

Conference Presentation

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Chikaaki Kodama, Mikiyasu Yamaji, Hiroshi Kitahara, Akira Hokazono, Shigeki Nojima, Piyush Pathak, Kimiko Ichikawa, Jac Paul Condella, Michel Cote, Ya-Chieh Lai, and Philippe Hurat "Transistor profiling for quantitative evaluation of variability in transistor characteristics due to layout dependent effects (LDEs)", Proc. SPIE 12954, DTCO and Computational Patterning III, 1295403 (10 April 2024); https://doi.org/10.1117/12.3010201

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