This PDF file contains the front matter associated with SPIE Proceedings Volume 12958, including the Title Page, Copyright information, Table of Contents, and Conference Committee information.

In this paper, we first present a brief review of the advanced-node logic device technology development and its key bottleneck/component processes using the existing lithographic capabilities. It is shown to be feasible to evolve into the GAA era with the minimum change of current FinFET process and a minor refining of previously reported Forksheet structure. The concept of hybrid-channel devices is raised which is not only promising for 3D vertical integration, but also offers an optimal tradeoff between device performance and power/leakage. To address the fabrication challenges, a mandrel/spacer engineering based patterning and metallization technology is proposed and its process development results are reported. This patterning & metallization technique can be applied to fabricate advanced logic and SRAM circuits with significantly enhanced pattern density. It is based on the self-aligned multiple patterning (SAMP) wherein either an alternating arrangement of different materials (with high etching selectivity) or multi-color layer decomposition (i.e., splitting of metallization process) is utilized to solve the edge-placement-error (EPE) issue. In particular, we explore various schemes of self-aligned triple patterning (SATP) to identify the potential solution to ensure a satisfactory profile control of the consecutively formed spacers. Moreover, this technique can incorporate rigorously self-aligned vias & cuts (SAVC), and accommodate a metal-layer division (MLD) to split the neighboring metal lines into two vertically staggered layers with their coupling capacitance significantly reduced. The tested metal Ru allows a direct dry etching, which offers a metal recess capability to enable an alternating-material coverage of neighboring metal wires by two different hard masks such that a selective etching can be applied to form rigorously self-aligned vias. Our early-stage process development is focused on SATP process optimization, fabrication of two simplified grating structures, material screening for appropriate etching selectivity, and metal-layer-division realization. Potential processing challenges such as Ru trench-filling quality and scaling issues of SAVC technology for advanced IC manufacturing will also be discussed.

In semiconductor manufacturing, the selective removal of the carbon mask after etching has become increasingly challenging with the introduction of Gate-All-Around (GAA) technologies. This transition has brought greater procedural complexity, necessitating more process steps to accommodate intricate and vertically structured designs. Consequently, there arises a need to reassess the appropriateness of traditional methods. Traditionally, the process relied on high RF power plasma to eliminate the carbon mask, resulting in the generation of large quantities of ions that could potentially compromise the integrity of thin film materials. As materials refine and designs require increased vertical scaling, associated risk factors are accentuated. Over-cleaning leads to ion damage, exemplifying the limitations in enhancing device performance. To overcome these challenges, an innovative selective mask removal (SMR) technology has been developed using Metastable Activated Radical Source (MARS). Utilizing MARS, radicals derived from hydrogen or oxygen exhibit lower energy levels, minimizing material damage on the wafer surface during the SMR process. This revolutionary technique significantly reduces the thickness of native oxide layers after SMR, lessening electrical resistance in critical processing steps and enhancing device performance. Furthermore, it enables improved surface passivation strategies, preventing the formation of native oxide and enabling multivalent passivation. These advancements mark a significant step in reducing pattern-induced damage in the GAA era, aligning with sustained progression in line with Moore's Law.

Nanosheet device architectures such as complementary FET (CFET) are candidates to replace FinFET, improving device performance while allowing a higher density of devices for a similar footprint. Two main challenges can be highlighted in the definition of the active area (AA) patterning for CFET. First the presence of stacked nanosheets generates the need for a higher aspect-ratio compared to FinFET. Secondly, the nanosheets layers, composed of silicon and silicon-germanium with varied thicknesses and concentrations, require new approaches in terms of process definition and control. The first results of an active area patterning for a full CFET device have been demonstrated at imec. Thicker nanosheet stacks are patterned opening the path to the creation of a complete CFET device.

In conventional gate-all-around FET architecture, p-type and n-type devices are stacked on top of each other on separate devices. In Complementary FET (CFET) architecture, n-MOS and p-MOS devices are stacked in the same device on top of each other. This allows for reduction in footprint and power consumption. One of the most high aspect ratio (HAR) patterning in CFET processing comes from patterning of the gate spacer, followed by nanosheet (NSH) patterning. The HAR Spacer Source/Drain cavity area is a Si/SiGe/Dielectric superlattices bringing quite a few patterning challenges. This work discusses the challenges for the spacer opening, optimization of the profile of the source drain (SD) cavity and strategies to improve selectivity with the gate hard mask (HM). The first patterning challenge includes etching of a superlattice consisting of numerous materials, including dielectrics, while maintaining selectivity to HM. This means switching of chemistries to accommodate the patterning of these multilayers. Secondly, this patterning step needs to be highly selective to the gate HM to allow enough margin for downstream processes. The patterning step also needs to deliver vertical cavity profile. All these challenges require us to explore complex etch processes including in-situ isolation, passivation, and other etching sequences. The results and challenges for a fully patterned spacer & SD cavity as demonstrated at Imec are presented in this proceeding.

This paper presents a new patterning scheme that allows self-alignment of active area contacts at different z-elevations. This patterning approach can be used for various types of 3D logic and memory devices. From an incoming structure using a stack of materials with different etch selectivity, some local metal braces are first introduced at certain targeted elevations and provide a first level of contact to active device materials. The brace formations require diverse etch selectivity for the selected dielectric materials, ultra-conformal metal deposition techniques for use on buried/covered structures, and anisotropic metal etching steps. A second level of contact is then made to access those braces by using via and cavity etches followed by metal fill. This multi-level contact patterning technique is further described in this paper by first using a generic example, and then by looking at two specific applications for logic and memory, with new CFET and staircase contacting schemes, respectively.

This work presents a process optimization study of 18nm metal pitch (MP) semi-damascene interconnects with fully self-aligned Vias (FSAV) using SEMulator3D^® virtual fabrication coupled with silicon data. Simulation was used to early identify process failures and avoid via opens found on silicon, and to ensure process manufacturability. A full predictive virtual model was calibrated against silicon data to predict the complete process flow from the M2 module to the via module. A process sensitivity analysis was performed to simulate process variability impact on via resistance performance. The simulation identified process parameters and corresponding process windows that need to be controlled to avoid via opens and ensure process manufacturability.

We performed a multi-step process optimization for high-aspect ratio etching using a Monte-Carlo based etching process simulation by solving the inverse problem. In this simulation, physical and empirical models are combined to provide a surface reaction model with response process knobs to achieve high accuracy within a short calculation time. We constructed a physical model for surface reactions which includes physical sputtering, chemical sputtering, radical deposition, surface modification by radicals, and thermal isotropic etching. We also updated the physical model to accommodate equipment parameters on the basis of experimental data. In this paper, we optimized 2-step recipe parameters including step time, low frequency RF power, O₂ flow rate and C₄F₈ flow rate. This yielded conditions for achieving straighter profiles. Furthermore, we experimentally verified that one of the proposed recipes has a better profile than that of the baseline condition. We achieved a straighter profile by optimizing multiple parameters with different bottom vs. bow sensitivity and by appropriate multi-step control.

We discuss the process integration to manufacture a spatial light modulator (SLM) device for application in mixed and augmented reality. The MEMS-part of the device is integrated on an external 180nm CMOS. The SLM consists of an 8MPixel micro mirror array with a pixel size of 4μm x 6μm. To provide the vertical strokes necessary for RGB color image generation, a comb-drive actuator concept was developed. Besides the yoke and the stator of the comb-drive, the actuator uses a double spring structure to reduce tilting of the mirror and other stress-induced effects. At the beginning of the product development we used iLine-lithography only, while later for the final device we switched to KrF-lithography to provide the necessary feature size down to 200nm as well as better CD-uniformity and overlay specification. We describe the process development, with focus on the lithography and etching processes for the actuator. Especially the different processes for patterning the Titanium-Aluminum structures of ultra-thin springs as well as the yoke and the stator with their high aspect ratios, which are specific for MEMS processing. Finally we achieved post-etch CD-uniformity <10nm per wafer for all metal structures as well on-product-overlay accuracy <15nm.

Metalenses are flat devices that focus and manipulate optical waves. Unlike reflective and refractive optics, metalenses rely on phase shifts introduced by subwavelength metastructures. Demonstrate the cost and performance impact of using manufactured metaatoms from two lithography processes to design and manufacture metalenses. Design two types of metalenses, the first type (ideal) uses an ideal design made up of square metaatoms. This lens design is then simulated using both 193nm and 248nm lithography processes. The second type (manufacture-aware) uses a design that is built around metaatom profiles produced by the corresponding lithography process (193nm and 248nm respectively). By comparing the performance of these two approaches (ideal and manufacture-aware) we demonstrate the process performance impact can be reduced. Comparing 193nm and 248nm processes show a up to a 27% difference in monochromatic metalens performance for a design derived from ideal metaatoms. However, by simulating manufactured metaatoms and using them in the design stage, manufactured metalens performance returns to within 7% of ideal. When designing with manufactured metaatoms rather than ideal metaatoms, metalens performance is similar between both 193nm and 248nm processes and manufacture-aware design makes either process viable for visible-light metalens manufacturing.

In a complementary FET (CFET), n- and p-type transistors are stacked on top of each other to enable device scaling. This stacking approach requires very high aspect ratio vertical feature pattering, namely, active gate, spacer source/drain cavity and contact patterning. We report contact trench patterning and plasma etch process development for contacting bottom and top transistors relevant to middle-of-line (MOL) integration in monolithic nanosheet based CFET. First, deep trenches (M0) with aspect ratio (AR) ~13 to 15 are etched into SiO₂ dielectric layer between tall gates for routing bottom device. After the formation of bottom device, MOL contact patterning (M0T, AR ~8 to 9) for top device is performed. The main etch challenges are to preserve gate and gate spacer (SiN) and achieve good depth uniformity, especially when the M0 trench CD is reduced at tight pitches. At pitch 50nm, M0 etch development results are shown for four different etch processes (named as Etch Recipe 1 to 4) in which M0 etch depth is increased gradually targeting minimal SiN loss. To reduce gate spacer (SiN) loss, fluorocarbon plasma passivation and hydrocarbon polymer deposition step is used during M0 trench patterning.

The wet etching of silicon (Si) is one of the most fundamental processes for the semiconductor industry. Although its etching kinetics on bulk Si surface have been thoroughly investigated, the kinetics of Si wet etching has yet to be fully addressed in nanoconfinements. Herein, we report the systematic study of potassium hydroxide (KOH) wet etching kinetics of amorphous-silicon(a-Si)-filled nanochannels. We discovered a nonlinear confinement dependence between the etching rate and the nanochannel dimension: the etching rate would increase with the increase in nanochannel height and then, gradually reaching a flat rate plateau. Our results provide new insights into the kinetic study of reactions in nanoconfinements and will shed light on etching process optimizations in industrial applications.

Microchip downscaling has been one of the main drivers on the semiconductor industry to enable faster, more efficient, and compact microchips, greatly broadening their range of applications, like the Internet of Things, smart mobility, artificial intelligence and 5G, among others. Aside from transistor scaling, the Back End of Line (BEOL) interconnection network, which transfers power and signals from and into the transistors, must also be scaled down consequently. The scaling requirements have surpassed the maximum resolution achievable by any lithographic technique by solely relying on direct printing. In the case of low numerical aperture, Extreme UV (low NA EUV), the most advanced, commercially available lithography technology, printing line/space structures below pitch 30nm (P30) is extremely challenging. However, 3nm and newer nodes require BEOL line space structures with P26nm or narrower, in particular for the M2 layer. It is here where multipatterning techniques come into play. Self-Aligned multipatterning techniques allow to divide by a factor of two (double patterning, SADP), four (quadruple patterning, SAQP) or even eight (octuple patterning, SAOP) the pitch printed at lithography level, easing the lithography requirements. However, with multipatterning, there comes a risk that not all interconnect lines would be patterned with equal dimensions, which would introduce resistance and capacitance variations across lines that theoretically should be equivalent. Hence, all multipatterning techniques require a precise control of each of the fabrication steps to guarantee that all lines and spaces present the same dimensions, i.e., a balanced patterning with no pitch walking. The target of our work is to find the fabrication parameters that lead to the lowest pitch walking, roughness and defectivity conditions on EUV SADP patterning (eSADP) at P21nm structures with 10.5nm metal line Critical Dimension (CD). Thus, we carried out a set of experiments where the printed lithography line CD and the spacer thickness values are swept on 300mm silicon wafers. Then, we analyze the patterning performance at different stages of fabrication to see the evolution of line and space CDs, roughness and defectivity values to determine the best candidate for P2 nm eSADP patterning.

The etch characteristics of Ir thin films were investigated in an inductively coupled plasma chamber, using a variety of chlorine gas chemistries, which included Cl₂/Ar, Cl₂/O₂/Ar, and BCl₃/Ar, as well as fluorine-based plasmas consisting of mixtures such as SF₆/Ar, SF₆/He, NF₃/Ar, and CF₄/O₂. Under our experimental conditions, we found that the etch rates of Ir were considerably faster in fluorine-containing plasmas (~30nm/min) compared to chlorine-based mixtures (<15nm/min). The patterning of 100nm line/space features has been demonstrated using an organic mask. Although they show the fastest etching rates, SF₆-based plasmas result in significant redeposition. In contrast, etching in CF₄/O₂ leads to etch profiles that are free of redeposition or residues. The poor selectivity of the mask over Ir under the different tested conditions results in shallow sidewall angles, hence highlighting the need for an alternative mask.

The lateral gate-all-around (GAA) field effect transistor is considered to be the most promising candidate for the next generation of logic devices at the 3nm technology node and beyond. SiGe plays an important role as a sacrificial layer in the GAA device, which requires isotropic etching, and the quality of the etching has a critical impact on the device performance. However, there is no definite scheme in the industry for the choice of etching method. In this paper, we choose two etching methods: CP(Inductively coupled Plasma) and RPS (Remote Plasma Source) etching according to the presence or absence of particle incidence. The profile and etching effect of the two etching methods are analyzed by PEGASUS simulation software. The presence or absence of particle incidence has different effects on the damage of the structure, the inconsistency of etching amount and the reflection of the particles on the Si surface. Compared with ICP etching, the optimization of RPS etching on etching damage and etch amount consistency is verified by TEM and roughness characterization . And through the extraction of MOSCAP capacitance, it is found that the density of interface states(Dit) after ICP etching is 3.5 times higher than that of RPS etching.

Self-aligned double patterning scheme is the dominant technique which is widely adopted in semiconductor industry to achieve finer patterns before extreme ultraviolet (EUV) lithography volume production is available. The critical dimension (CD) for the key structures fabricated from SADP flow, normally referred to as Bitline (BL) or Wordline (WL), is crucial to enable the microcircuitry to operate properly. Therefore, the CDs’ precise control receives substantial attention as a key indicator to demonstrate the manufacturing process capability in quality management. This paper presents an in-depth analysis on BL CDs’ variation control from SADP scheme, followed by several applicable approaches for process capability improvement across multiple modules through conceptual and experimental illustration, which could serve as a guideline for semiconductor manufacturing industry.

Low-temperature kinetic plasma simulations using particle-in-cell (PIC) and Monte Carlo methods (DSMC/MCC) for the chemistry can provide many advantages over the more popular fluid simulations, including detailed information about the ion energy and angular distribution functions that are critical for plasma processing. In this presentation, two different types of simulations illustrating the power of kinetic modeling are demonstrated. The first is a macroscopic-scale simulation of an inductively coupled plasma (ICP). We demonstrate how implicit methods can make these challenging simulations feasible, and show that our numerical model captures salient physical effects (inductive coupling, sheath formation, plasma generation, etc.) of the ICP discharge. Efforts to hasten the convergence of these simulations to steady-state and to improve their predictive capabilities are also summarized. Secondly, we outline ongoing work to develop microscopic feature-scale simulations of a through-silicon-via etch process, obtaining potential boundary conditions and incident particle fluxes within the feature from larger-scale kinetic sheath computations. For both simulation types, ion energy-angle distributions at the wafer surface, electron kinetics, and the detailed physics of the sheath and presheath can be computed by our numerical model.

Thermal Atomic Layer Etching (ALE) has received attention in recent years as an emerging semiconductor fabrication technique, as the device dimensions are scaling down to only a few nm. Thermal ALE has the ability to etch material isotropically, which is especially useful for high aspect ratio features. Copper ALE is of considerable interest since Cu is still the metal of choice for interconnects. In order to etch a Cu thin film conformally, the first step (surface oxidation) needs to be carefully controlled. Currently used oxidants, like ozone, hydrogen peroxide or oxygen plasma tend to damage the copper surface and oxidize it up to a few nm deep. These are undesirable outcomes for ALE, because the surface should remain as uniform as possible post oxidation, so that the etch step yields a smooth and conformal Cu surface. Therefore, there is a need for more tunable oxidants which allow for better control of the oxidation strength and depth of Cu thin films. In this paper, we report new, mild oxidants for Cu ALE. The oxidation strength of these reagents has been probed by in-situ x-ray Absorption Spectroscopy and one of them has been tested in real ALE conditions together with a known etch ligand (hexafluoroacetylaceton) and probed by in-situ QCM.

The synthesis, spectroscopic properties, and suitability for use as precursors in atomic layer deposition (ALD) processes are described for the ZrCp₃ and HfCp₃. ZrCp₃ was prepared by a literature procedure entailing reduction of ZrCp₄ with potassium graphite and was isolated as brown crystals in 34% yield. HfCp₄ was isolated in 57% yield as yellow-brown crystals by a similar route employing reduction of HfCp₄ with potassium graphite. ZrCp₃ and HfCp₃ showed broad paramagnetic resonances in the ¹H NMR spectra that were centered at δ 6.2 and 6.0ppm, respectively, which are assigned to the cyclopentadienyl hydrogen atoms. Additionally, the ¹H NMR spectra of the ZrCp₃ and HfCp₃ crystals revealed resonances arising from the diamagnetic complexes Cp₃ZrH and Cp₃HfH, which are proposed to arise from hydrolysis of ZrCp₃ and HfCp₃ by traces of water in the NMR solvent. The identities of ZrCp₃ and HfCp₃ were established by determination of their x-ray crystal structures, which exactly matched previously reported molecular structures. Thermogravimetric analyses of ZrCp₃ and HfCp₃ were conducted to assess their volatilities and thermal stabilities. ZrCp₃ showed the onset of mass loss at about 125 °C and revealed a single-step evaporation up to about 225 °C, at which point decomposition limited further mass loss. Mass loss for HfCp₃ started at about 150 °C and continued up to about 270 °C, at which point decomposition limited further mass loss. ZrCp₃ and HfCp₃ decomposed extensively during preparative sublimation experiments at 0.5 Torr, and do not appear to have promising properties as ALD precursors.

The semiconductor industry is aware of its high resource consumption and overall impact on the environment and is working to minimize it. Especially, the use of perfluorocarbons (PFC) during the dry etching and deposit steps of device manufacturing is a major concern because of the extremely high global warming potential (GWP) and lifetime of most of those compounds. Consequently, plasma etching significantly contributes to CO₂ emissions for sub-28nm technologies on Scope 1 and 2 emissions. Currently, CEA-Leti is developing a 10nm node on FDSOI (Fully Depleted Silicon On Insulator) technology. In this framework, we present Life Cycle Assessment (LCA) of etching processes for FDSOI transistor technologies. A comparison of impacts between the 28nm node and 10 nm one is then conducted for FEOL and MEOL processes. Finally, based on these results, some eco-innovation proposals are discussed.

Future advanced semiconductor manufacturing processes are introducing significant patterning challenges. These challenges are coming together with additional requirements for sustainable, low Global Warming Potential/ low toxicity /low fine particle emissions. As a result, new solutions in terms of process integrations, molecules used for patterning modules, and overall stack of materials will have to meet those requirements while staying compatible with high-volume manufacturing (cost, availability, throughput, and overall patterning performance). Although specific process steps such as capacitor patterning for DRAM or 3D NAND high aspect ratio oxide etch are heavily scrutinized steps in terms of emissions and patterning challenges, many applications, including logic, integrate hundreds of steps where the patterning of 10 to 30nm-thick layers requiring fluorine-containing gases. Although independently accounting for a modest amount of emissions, their sheer counts makes them a major contributor to CO₂ equivalent emissions. In this work, the cumulative impact of these low aspect-ratio patterning steps will be modelled through the imec.netzero program model. Then, the impact of a few sustainability-optimized solutions, such as low temperature etching for ultra-thin layer or stack optimization will be assessed.

Per- and polyfluoroalkyl substances or PFAS have faced increased scrutiny because they are environmentally persistent and certain PFAS have also been found to be bioaccumulative and toxic. In recent years, PFAS chemistries have been grouped as a class based on chemical structure rather than physical and chemical properties or environmental and human health considerations. This class definition has brought into scope many fluorocarbons found in semiconductor manufacturing, including the fluoropolymers used to ensure safe handling and distribution of chemicals and gases, as well as perfluorocarbon (PFC) and hydrocarbon (HFC) gases used in plasma etch processes. This paper will present a historical perspective of the semiconductor industry’s efforts to reduce F-GHG consumption and emissions. It will conclude with an overview of the work of the Semiconductor PFAS Consortium and their plasma etch and deposition working group.

Over the past few years, numerous countries and semiconductor manufacturing entities have unveiled their commitments to achieving net-zero carbon emissions by 2050 or even sooner. When it comes to manufacturing chips, plasma etch processes contribute significantly to emissions, especially in dielectric etching. These processes typically involve the use of high global warming potential (GWP) fluorocarbon gasses like CHF₃, CF₄, and CH₂F₂. Air Liquide's research and development (R&D) endeavors have led to the creation of multiple alternative etch chemistries for SiN and SiO₂ etching applications that boast remarkably low GWPs. Despite strides in developing these alternative chemistries, accurately forecasting the gases emitted post-plasma remains elusive. The complexities inherent in the breakdown and recombination processes within the plasma make it challenging to predict the specific emissions, regardless of whether the gas introduced into the plasma etch chamber carries a high or low GWP. This research showcases the utilization of Fourier Transform Infrared Spectroscopy (FTIR) to analyze and measure the emission gas stream from the plasma etch chamber. Moreover, the innovative chemistries developed by Air Liquide have exhibited enhanced etch performance while resulting in lower CO₂ equivalent emissions compared to the current baseline in dielectric etching.

Bowing is one of plasma etching effects that negatively impact device performance. Although there has been plenty of research work on micro-feature surface etch modeling to investigate bowing effect, limited research has been reported on the influence of hardmask morphology on bowing effect. In this paper, we present a plasma etching model based on Monte Carlo simulation with cellular method in order to simulate the feature profile evolution of etching process in nano-scale. The relationship among hardmask angle, open CD and distribution of reflected ion flux on the sidewall from the opposite hardmask was calculated. The reflected ion flux was heavily concentrated in the upper part of the sidewall in the case of a tapered hardmask, and this was the main mechanism of the bowing formation. This model considers chemical reactions and a novel particle reflection algorithm which is a prominent mechanism. This model is capable of reproducing the feature in periodic dense trenches with dimension of tens of nanometers. The hardmask morphology considered in our study includes hardmask angle (θ) and pattern (CD and pitch). As the hardmask angle decreases, the bowing becomes severe, when CD equals to 90nm and θ equals to 70°, the bowing deviation (D=(W-CD)/2) and relative deviation (Δ D=D/CD×100 %) are 23.86nm (26.51 %). In contrast, as the CD increases, the bowing becomes slight. However, bowing moves toward the bottom of the hole as the CD increases. When CD equals to 150nm and θ equals to 70°, the bowing deviation is 18.95nm (12.63 %). Accordingly, a vertical hardmask is very important for a small CD trench.

In gate-all-around nanosheet (GAA-NS) transistor manufacturing, the SiGe layer plays an important role as a sacrificial layer, requiring precisely controlled and highly selective isotropic etching. In our previous work, we proposed a novel isotropic selective quasi-atomic layer etching (quasi-ALE) method based on O₂ plasma self-limiting oxidation and CF₄/C₄F₈ self-limiting selective etching. A vertical nanowire transistor with a diameter less than 20nm and an accuracy error less than 0.3nm has been developed. In this paper, we adopt this method to cavity etching of horizontally stacked nanosheets, using an ICP source to perform self-limiting oxidation of the SiGe layer followed by self-limiting selective removal of oxide (a two-step self-limiting cycle) to form inner spacer cavity. Experimental results show that compared with the strong dependence of the etching amount on SiGe thickness and Ge composition in traditional ICP dry etching, the quasi-ALE technology tends to weaken this size and concentration loading effect due to the self-limiting of each cycle reaction. In addition, we also demonstrated the latest progress in corresponding ALE simulation using a commercial feature-scale plasma process simulator named PEGASUS. The simulation results show that the SiGe etching amount per cycle (EPC) is about 0.3nm, which is basically consistent with the experimental results. This quasi-ALE method demonstrates promising performance for preparing GAA device channels, nanosensors, and other application in future.

Atomic layer deposition (ALD) technology is a self-limiting film deposition process that grows films on substrates through repeated process cycles of precursor dosing, purge, co-reactant dosing and purge. This technology is widely utilized in advanced technology node processes due to its merits of excellent step coverage and atomic scale film thickness control. However, as the industry moves to three-dimensional (3D) device architectures, ALD faces emerging challenges such as the bottle neck phenomenon in extremely high aspect ratio structure with nanometer scale trench or hole open. ALD modeling provides insights into the underlying mechanisms and help engineers optimize the process. There has been research on different kind of ALD process models on film conformity, growth profile and saturation behavior at multiscale from reactor to micro-feature and molecular level. Angel Yanguas-Gil et al. proposed a reactor scale model which discussed the ideal and non-ideal self-limited processes in a cylindrical and a 300 mm wafer cross-flow reactor. Adomaitis et al. presented a multiscale model to describe the reactant transport in a high aspect ratio nanopore and growth of ALD film based on continuum and Monte Carlo model. In this work, we propose an ALD model in order to simulate the spatial ALD process, coupling with surface reaction kinetics theory and hydrodynamics model. Firstly, we analyze and model the adsorption process of precursor molecules and co-reactant molecules, as well as their transport mechanism in ALD reactor chamber. Secondly, we discuss how the substrate temperature, precursor and co-reactant partial pressure, and reaction probabilities influence coverage distribution and growth per cycle in spatial ALD process. This model enables the possibility of spatial ALD process parameter optimization in an efficient and economy way.

Three-dimensional (3D) architectures have become main stream for the advanced node logic and memory devices, such as the gate-all-around field effect transistors (GAAFET) and 3D dynamic random access memory (3D DRAM). These devices feature with stacked structure offers higher integration, better device performance and lower power consumption. However, the manufacturing of such devices needs high aspect ratio (AR) feature processing which brings challenges to conventional thin film deposition process such as chemical vapor deposition (CVD). SiN is a common barrier and spacer material and usually grown by CVD with a gas mixture of SiH₄/NH₃/N₂. In this work, we conduct simulations of SiN CVD process in deep trenches to investigate the thin film step coverage dependence on process conditions and AR. We adopt the reaction-diffusion theory to develop the surface growth model of SiN deposition and set a few semi-empirical mechanism parameters to calibrate the model with experimental results. Simulation results show that in the substrate trench with 50nm open CD and AR of 5, the film deposition step coverage becomes better as the fluxes of neutrals increases, corresponding to lager f_neu value. Simulations also suggest that with trench depth fixed at 250nm, as the AR of the trench increases, the overall deposition rate in the trench decreases. As the AR increases, the density of the reactant species such as radicals and ions decrease and the diffusion-limited phenomenon appear, which further reduces the reaction rate at the bottom of the trench.

Plasma atomic layer etching (ALE) for SiO₂ and Si₃N₄ and reactive ion etching (RIE) for SiO₂ with hole-patterns were developed using C₄F₈ and the low global warming potential gases of perfluoroisopropyl vinyl ether (PIPVE) and perfluoropropyl vinyl ether (PPVE). The ALE windows of SiO₂ and Si₃N₄ were in the range of 50.0-57.5 V for all precursors. Etch per cycle of SiO₂ was determined to be 5.5Å /cycle (C₄F₈), 3.3Å /cycle (PIPVE), and 5.4Å /cycle (PPVE), all lower than that of Si₃N₄. PPVE reduced global warming emissions by 49%, demonstrating better vertical etch profiles in RIE compared to C₄F₈.