32-bit digital optical computer: a hardware update

Peter S. Guilfoyle; Dennis R. Pape; James A. Carter III; Richard V. Stone

doi:10.1117/12.21248

1 September 1990 32-bit digital optical computer: a hardware update

Peter S. Guilfoyle, Dennis R. Pape, James A. Carter III, Richard V. Stone

Author Affiliations +

Proceedings Volume 1296, Advances in Optical Information Processing IV; (1990) https://doi.org/10.1117/12.21248
Event: 1990 Technical Symposium on Optics, Electro-Optics, and Sensors, 1990, Orlando, FL, United States

Abstract

Such state-of-the-art devices as multielement linear laser diode arrays, multichannel acoustooptic modulators, optical relays, and avalanche photodiode arrays, are presently applied to the implementation of a 32-bit supercomputer's general-purpose optical central processing architecture. Shannon's theorem, Morozov's control operator method (in conjunction with combinatorial arithmetic), and DeMorgan's law have been used to design an architecture whose 100 MHz clock renders it fully competitive with emerging planar-semiconductor technology. Attention is given to the architecture's multichannel Bragg cells, thermal design and RF crosstalk considerations, and the first and second anamorphic relay legs.

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Peter S. Guilfoyle, Dennis R. Pape, James A. Carter III, and Richard V. Stone "32-bit digital optical computer: a hardware update", Proc. SPIE 1296, Advances in Optical Information Processing IV, (1 September 1990); https://doi.org/10.1117/12.21248

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