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9 February 2024 Fault tree generation and analysis based on extended SysML model
Yiping Wang, Tiantian Wang, Xinglong Li, Xianghu Wu, Kuanjun Liu
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Proceedings Volume 13073, Third International Conference on High Performance Computing and Communication Engineering (HPCCE 2023); 130730I (2024) https://doi.org/10.1117/12.3026535
Event: Third International Conference on High Performance Computing and Communication Engineering (HPCCE 2023), 2023, Changsha, China
Abstract
This paper proposes an extension of the SysML safety semantic approach to address the lack of safety and reliability semantics and the support for safety and reliability analysis of the model in SysML. On this basis, fault tree generation and analysis are performed. The method first adds semantic information about fault tree and redundant module to the model using the Stereotype extension mechanism, integrating design data and safety data through an extended configuration file in the SysML model. Secondly, sub-mode decomposition of Internal Block Diagram is conducted, and fault mode recognition is described in relation to fault tree mapping. Based on this, a search is conducted on the SysML model to obtain necessary information for fault tree generation, followed by an analysis of the generated fault tree.
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Yiping Wang, Tiantian Wang, Xinglong Li, Xianghu Wu, and Kuanjun Liu "Fault tree generation and analysis based on extended SysML model", Proc. SPIE 13073, Third International Conference on High Performance Computing and Communication Engineering (HPCCE 2023), 130730I (9 February 2024); https://doi.org/10.1117/12.3026535
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KEYWORDS
Safety
Semantics
Design
Model based design
Embedded systems
Reliability
Systems engineering
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