Edge-side load prediction analysis method based on hardware acceleration

Yuqiang Yang; Qiming Zhao; Lei Li; Pengfei Lu

doi:10.1117/12.3037542

27 September 2024 Edge-side load prediction analysis method based on hardware acceleration

Yuqiang Yang, Qiming Zhao, Lei Li, Pengfei Lu

Author Affiliations +

Proceedings Volume 13275, Sixth International Conference on Information Science, Electrical, and Automation Engineering (ISEAE 2024); 132751W (2024) https://doi.org/10.1117/12.3037542
Event: 6th International Conference on Information Science, Electrical, and Automation Engineering (ISEAE 2024), 2024, Wuhan, China

Abstract

The data for load forecasting is characterized by randomness and burstiness, and it is often required to have an accurate and fast load forecasting response in integrated energy and power market trading. Therefore, a solution is proposed for this scenario, which is based on an edge computing approach using an algorithmic model combining variable modal decomposition (VMD) and long and short-term memory network (LSTM). Because of the use of VMD, it is necessary to train multiple LSTM networks and complete the forward inference as simultaneously as possible, and the parallelization feature of Field Programmable Gate Array (FPGA) is considered for hardware acceleration design. First, edge computing has low latency, fast response, etc., and the data is decomposed into multiple intrinsic modal functions using variable modal decomposition so that the LSTM models can be trained separately to better handle nonlinear and nonstationary data. This is used to achieve computational acceleration and hardware resource consumption optimization. The results of the comparative analysis show that the edge-based VMD+LSTM model hardware architecture exhibits excellent performance in terms of computational speed for load prediction.

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

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Yuqiang Yang, Qiming Zhao, Lei Li, and Pengfei Lu "Edge-side load prediction analysis method based on hardware acceleration", Proc. SPIE 13275, Sixth International Conference on Information Science, Electrical, and Automation Engineering (ISEAE 2024), 132751W (27 September 2024); https://doi.org/10.1117/12.3037542

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KEYWORDS

Data modeling

Field programmable gate arrays

Computer hardware

Education and training

Data transmission

Design

Modal decomposition

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