Rapid debug of yield and performance bottlenecks within the UltraSPARC-I microprocessor

Aswin Mehta; Greg Billus

doi:10.1117/12.250839

12 September 1996 Rapid debug of yield and performance bottlenecks within the UltraSPARC-I microprocessor

Aswin Mehta, Greg Billus

Proceedings Volume 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II; (1996) https://doi.org/10.1117/12.250839
Event: Microelectronic Manufacturing 1996, 1996, Austin, TX, United States

Abstract

We have developed a set of analysis tools to accelerate root-cause understanding of any UltraSPARC^TM-I microprocessor manufacturing process or design problems encountered on the path to volume manufacturing ramp. We also use these tools to understand root-cause of yield or performance limitations. The custom hardware and software developed to support UltraSPARC^TM-I debug is presented, followed by a discussion of our debug methodology. We conclude with an example use of the tools and methods presented to analyze and resolve an actual problem experienced during UltraSPARC^TM-I manufacturing start- up.

Citation Download Citation

Aswin Mehta and Greg Billus "Rapid debug of yield and performance bottlenecks within the UltraSPARC-I microprocessor", Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); https://doi.org/10.1117/12.250839

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