Reconfigurable-hardware-based digital signal processing for wireless communications

Kevin J. Page; Jeanette F. Arrigo; Paul M. Chau

doi:10.1117/12.279508

24 October 1997 Reconfigurable-hardware-based digital signal processing for wireless communications

Kevin J. Page, Jeanette F. Arrigo, Paul M. Chau

Proceedings Volume 3162, Advanced Signal Processing: Algorithms, Architectures, and Implementations VII; (1997) https://doi.org/10.1117/12.279508
Event: Optical Science, Engineering and Instrumentation '97, 1997, San Diego, CA, United States

Abstract

This paper presents, index mapping, a technique to efficiently map a widely used class of digital signal processing algorithms onto a space/time paradigm with immediate representation as the partitioning and scheduling map of a small, I/O efficient, hardware array. When applied to reconfigurable FPGA based hardware architectures with downstream sea-of-gates optimization methods, the resulting systems form a dynamic signal processing environment with the best mix of performance and flexibility for wireless applications. Herein, index mapping is demonstrated with a mapping of the fast Fourier transform (FFT) onto an FPGA computing machine, the reconfigurable processor (RCP).

Citation Download Citation

Kevin J. Page, Jeanette F. Arrigo, and Paul M. Chau "Reconfigurable-hardware-based digital signal processing for wireless communications", Proc. SPIE 3162, Advanced Signal Processing: Algorithms, Architectures, and Implementations VII, (24 October 1997); https://doi.org/10.1117/12.279508

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