This passivation integrity study was initiated as part of a submicron integration development program. New processes were developed which reflect a shrink in the device geometry's and significant changes in processes and equipment used. An immediate concern was the effect of these changes on the passivation integrity. To investigate these effects a series of passivation integrity tests were performed. Passivation failures were quantified via optical inspection and failure sources were identified by SEM analysis. The majority of the tests were performed on short flow processes (i.e. backend process flows consisting of 2 and 3 layer metal patterned structures). Full flow processes (integrated frontend and backend processes) were investigated on BiCMOS and CMOS technologies.

A BiCMOS device which was having low yield problem at sort was systematically analyzed. In this case the failure was delaying shipment and pressure ofreducing analysis time was extremely high. This paper presents a method employed to quickly identify the failure signature and localize the defect to a minimum area of the device. The physical defect, silicon fault/dislocation, found by TEM has been fully characterized and reported in this paper. It is believed that the information presented in this paper will be helpful for failure analysis and product personnel. Emission microscopy system since its creation in 1980's, has dramatically demonstrated its ability to reduce failure analysis cycle time by providing qualitative evidence of the suspected failure. Together with other failure analysis techniques such as OBIC, TEM etc. can put failure analysis to its full capability. This paper describes in details and demonstrates a successful application of the emission microscope to pinpoint the location of a dislocation defect that caused C-E leakage in a NPNtransistor. Both frontside and backside emission were performed and will be discussed in the paper. A quick sample preparation for backside emission is proposed.

The photoresist stripping process in passivation stage could induce the bonding pad surface corrosion (Figure-i). And the bonding pad surface corrosion rates will be accelerated if the chlorine concentration levels reach 5 to i 0 ppb in the cleanroom environment. The facility hookup of the exhaust pipelines and the cross contamination between the different airflow system has been identified to be critical regarding the chlorine concentration levels. In order to improve the pad surface susceptibility toward the chlorine molecules induced pad surface corrosion, the CF4 treatment is proposed with excellent passivation and replacement effects.

This paper describes a method for the statistical characterization and modeling of spatial variations of thin film thickness across a wafer lot over multiple furnace runs. The method uses experimental thickness data to construct a simplified Karhunen-Loeve model that captures both deterministic and random nonuniformity variations. The model uses simple quadratic interpolation functions and a reduced number of random variables and permits calculations of distribution functions over different lot populations (wafer, die, point, etc.) The main advantage of this model is the retention ofspatial correlations that are essential for the accurate prediction ofparametric yield. The characterization method was applied to several thin films using a data set of 35,000 thickness measurements of LPCVD oxide, nitride, and polycrystalline silicon as well as thermal oxide. Run-to-run distributions for the random variables were estimated using three-year (1995-1997) historical rate data logged at the UM Solid State Electronics Laboratory (SSEL). Comparisons are presented depicting probability density functions (PDFs) extracted from the model and a Monte Carlo (MC) based estimator are in good agreement.

As semiconductor devices enter the deep sub-micron era, reliability has become a major issue and challenge in VLSI design. Among all the failure mechanisms, hot-carrier effect is one of those which have the most significant impact on the long-term reliability of high-density VLSI circuits. In this paper, we address the problem of minimizing hot-carrier effect during the technology mapping stage of VLSI logic synthesis. We first present a logic-level hot-carrier model, and then, based on this model, we propose a technology mapping algorithm for hot-carrier effect minimization. The proposed algorithm has been implemented in the framework of the Berkeley logic optimization package SIS. Our results show that an average of 29. 1% decrease in hot-carrier effect can be achieved by carefully choosing logic gates from cell libraries to implement given logic functions for a set of benchmarks. It has also been observed that the best design for hot-carrier effect minimization does not necessarily coincide with the best design for low power, which has long been considered as a rough measure for VLSI reliability.

It is widely recognized that interconnects will be the main bottleneck in enhancing the performance of future deep sub-micron VLSI designs. Interconnects do not "scale" well with decreasing feature sizes and therefore dominate the delays in the integrated circuit. In addition to RC delays, crosstalk noise also contributes significantly to the delays experienced by a signal. Interconnects are more susceptible to manufacturing defects and therefore affect the product yields significantly. Recently, several channel-routing based solutions have been proposed to minimize crosstalk noise and also enhance yield of the routing. While these approaches are effective, they do not provide maximum benefits as they are either constrained by a particular design methodology or are post-routing steps which have limited scope for significant improvement. Also, design for manufacturabiity objectives have not been fully exploited by VLSI CAD tools as they do not integrate seamlessly into the conventional design flow and the added overheads make it less attractive. In this paper, we propose a modified routing algorithm that maximizes yield and reduces crosstalk noise while using minimal area for the routing. The yield enhancement objective has been integrated into the routing phase as a preferred constraint (a constraint that will be satisfied only if the primary constraints of minimal area and wire length have been satisfied) and fits well into the conventional design flow. This enables the router to produce an output which provides maximum achievable critical area reduction for the given routing solution. Post-routing layout modification is also done with the objective of minimizing the interaction area between the interconnects by exploiting the gridless property of the router. The above algorithm is incorporated into GLITTER (the gridless, variable width channel router), and the results on channel-routing benchmarks are presented. These results show a significant reduction in the critical area achievable by using the proposed algorithm.

After final electrical tests of microchips, an additional visual inspection is performed to guarantee their long term reliability. This step is time consuming and highly labour intensive. To reduce costs, and to improve at the same time the defect density monitoring using a higher sampling rate, the final visual inspection performed manually by operators, is replaced by an automatic inspection. This paper illustrates how the high sampling rate of a automatic final inspection may be used for better defect monitoring through final insulator layers, monitoring underlying metal layers as well.

Statistical meirology was used to characterize the pad life in chemical mechanical polishing process. A special chip containing capacitor structures with dimensions laid out as per a fractional factorial design of experiment was used as a lest vehicle in this study. The wafer lot was separated into four splits and each split was polished at a different time depending on the wafer count since the last pad change in the chemical mechanical polishing system. Capacitance measurements were done on the test capacitors and the IMD thickness was determined from the 2D simulation of the capacitor. The wafer-level and die-level variations were determined using an application software program known as Variation Decomposition Analysis Program . The useful pad life can be determined by selecting the wafer count below which inter- and intra-die variations are allowable.

The expected number of wafers outs generated by fiscal weeks is used commonly to define the company budget. The traditional approach to determine this quantity has been so far, the use of static analytical tools like the spreadsheets in which the cycle time and fab yield variation is ignored. Both variables are treated as fixed inputs, disregarding consequently their non-deterministic nature. This special behaviour could cause an unexpected result in the throughput forecasted with important financial consequences. This paper proposes an alternative approach, based on the Monte Carlo method, to the static calculation and studies the expected variability in the number of outs when the cycle time and the fab yield are considered as variables randomly distributed. The expected variability and its dependence to the method elected -static and fixed vs. dynamic and variable- are studied.

The way in which dies are allocated within a wafer is the subject of this paper. Standard ways of doing it are based on a software program, mainly in-house built, that uses default values for all the variables and do not take into account, in a direct mode, the actual distribution of yield versus distance to wafer edge in the manufacturing line where the chip is to be manufactured. We present a novel Software System for die allocation in the wafer, that uses an empirically obtained Yield Distribution Function (which gives the normalized yield for every X Y coordinate over the entire wafer area). The software developed gives as output the optimum die allocation in terms of yield.

The comparative analysis of process machines in terms of yield related metrics (such as probe and E-Test data, process and particle data,. ..) is a source of a great deal of information for yield improvement. With this aim we published on SPIE's Microelectronic Manufacturing an Advanced Software System to detect machine-related yield limitors using a comparative analysis. This paper presents the natural expansion of that Software System by converting it into a more knowledge-based tool for fast yield loss detection on a semiconductor fab. The new System performs, in an automatic mode, the comparison among machines for every single step selected in the fabrication routing. The detection of statistically significative differences among machines at every step is performed using algorithms that incorporate the overall analysts experience on our fab. The output of the System allows a fast detection and reaction to yield issues, mainly to those that are still on the initial or baseline stages.

This paper addresses the integrated circuit industry needs for non-isothermal simulation in device reliability analysis, initial input factor sensitivity analysis and their software implementation. The key reliability issues are the hot-electron induced oxide damages and electro-static discharge (ESD) damages. The main purpose of this work is to provide a design aid tool to improve device reliability and performance. The reliability simulator developed in this work not only predicts designed device reliability, but also provides some information about the effect of manufacturing variations on reliability. This is accomplished by combining the statistical methodology with existing technology computer aided design (TCAD) tools. The design of experiment (DoE) technique can be successfully employed to analyze the effect of manufacturing variations on the SOT device reliability. As an example, the reliability analysis and the statistical analysis have performed on SOT MOS devices (partially depleted and fully depleted SOT) and submicron bulk-Si MOSFET's to verify the applied modeling method.

This paper reports a methodology that is able to reduce the "time to money for the IC Industry" by increasing the yield and reliability of devices fabricated in an immature process. This is achieved through both automated generation of redundant vias and methods of efficiently estimating the impact of such modification on the device yield. The approach consist of identifying non-redundant vias that are contained within a VLSI design together with a method ofgenerating associated redundant vias. The number of redundant/non-redundant vias before and after the modification procedure is efficiently estimated using a sampling technique. Hence, only a fraction of the device need be modified and analysed. This enables efficient comparison of different modification strategies, taking into account not only yield mechanisms that are improved but also those that may be adversely affected by the introduction of new vias and any associated conductor material.

Defect parameter extraction plays an important role in process control and yield prediction. A methodology of evaluating wafer level defect clustering will be presented to detect equipment specific particle contamination. For that, imaginary wafermaps of a variety of different chip areas are generated to calculate a yield-to-area dependency. Based on these calculations a Micro Density Distribution (MDD) will be determined for each wafer. The range and course of the MDD may indicate specific failures of equipment tools.

The hot-carrier degradation of pMOSFETs is affected by the sequence of bias conditions. Device parameter shifts under dynamic stresses can be different from those determined from DC stressing experiments. In particular, hole injection is enhanced when preceded by electron trapping, though subsequent electron trapping is not affected by hole injection. Sequences of electron trapping preceding hole injection and hole injection preceding electron trapping both enhance the rate of interface trap formation relative to that seen in single-bias, e.g. single-mode or DC, stressing experiments.

During plasma etch steps, devices are exposed directly to plasma and charge collection/deposition onto aluminum or poly damage gate oxides. This damage results in higher subsequent hot-carrier degradation. Here, the statistical variations in waler-level hot-carrier degradations are investigated. Interface-trap formation is shown to be independent of antenna size across a wafer, while bulk oxide trapping center density is found to be highly dependent on the antenna size and type.

Arc induced gate oxide breakdown in a plasma etching process was observed and its mechanism was analyzed in this paper. The gate oxide was broken during the poly4 etching process and the poly4 layer is O.8um high from the gate(polyl) layer. Since the broken gate oxide points were found scattered surrounding the arc occurrence point, it is assumed that excessively high electric field be generated near arc occurrence point, making the gate oxide broken. Generally, pattern deterioration by heavy ion bombardment has been observed around the arc point and believed to be the cause of low yields when arc phenomena occurs in the plasma etching process. It is found that any arc occurrence could cause dies to fail by breaking the gate oxide, even if the deteriorated pattern is not concerned with the active die circuits.

For reliability prediction in metallization structures the different migration mechanisms like electro-thermo- and stressmigration (due to mismatch of thermal expansion and elastic moduli) become more and more important. With numerical methods like the fmite element methode FEM, it is possible to determine the weakest part ofa metallization structure. In this paper the mechanical stress distribution as well as the mass flux and mass flux divergence due to electrical, mechanical and thermal effects will be investigated and correlated with measurements. In the investigations an unpassivated aluminum-meander test structure was used. For the aluminum meander structure the current density, temperature gradients and mechanical stress distributions were determined by fmite element simulations with the FEM-program ANSYS. The resistivity as well as the activation energy was determined by measurements. Based on the results ofthe simulations the mass flux due to mechanical stress were calculated and compared with the calculated electro- and thermomigration mass flux.

Particulate contamination deposited on silicon wafers is typically the dominant reason for yield loss in VLSI manufacturing. The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the defect location, size, material and the underlying IC topography. A rigorous topography simulator, METROPOLE, has been developed to allow the prediction and correlation of the critical physical parameters (material, size and location) of contamination in the manufacturing process to device defects. The results for a large number of defect samples simulated using the above approach were compared with data gathered from the AMD-Sunnyvale fabline. A good match was obtained indicating the accuracy of this method which provided a framework for developing contamination to defect propagation/growth macromodels. We have demonstrated that the understanding of defect transformation can be applied to early yield impact prediction.

When a reliability test ends in zero units having failed, traditional reliability calculations suggest that the estimated failure rate is also zero, assuming an exponential distribution. However, this is not a realistic estimate of the failure rate, as it does not take into account the number of units on test. In such cases, a reasonable approach is to select a failure rate that makes the likelihood of observing zero failures equal to 50%. In other words, we select a failure rate that carries with it a high probability of observing zero failures for a given reliability test'. In this paper we review this methodology and demonstrate how it has been implemented at Advanced Micro Devices (AMD) through a user friendly EXCEL based software application. Customized software tools such as this have led to increased awareness, productivity, and accuracy in reliability calculations at AMD.

This paper presents a computer algorithm for accurately counting the total number of possible yielding die sites on a wafer. This algorithm takes into account such variables as the X and Y die dimensions, the size and orientation of the wafer flat(s), the size of the non-yielding periphery zone, and the position of the die array relative to the center of the wafer. This algorithm can be used in conjunction with a variety of different yield models to increase each model's ability to predict accurate die per wafer yields. In addition to applications in yield modeling, this die counting algorithm may also be used as a tool for increasing yields or decreasing circuit layout cycle time. Several examples of these alternate applications are presented.