Paper
6 October 1997 Fast IP routing with VC-merge-capable ATM switches
Indra Widjaja, Anwar I. Elwalid
Author Affiliations +
Proceedings Volume 3233, Broadband Networking Technologies; (1997) https://doi.org/10.1117/12.290481
Event: Voice, Video, and Data Communications, 1997, Dallas, TX, United States
Abstract
Recent work on building fast IP routers has emphasized on integrating ATM switching with IP routing. One critical issue is concerned with ways to map IP routing information to ATM labels. VC merging allows many routes to be mapped to the same VC label, thereby providing a scalable mapping method that can support tens of thousands of edge routers. VC merging requires reassembly buffers so that cells belonging to different packets intended for the same destination do not interleave with each other. We investigate the impact of VC merging on the additional buffer required for the reassembly buffers and other buffers due to the perturbation in the traffic process. The main result indicates that VC merging incurs a minimal overhead compared to non-VC merging in terms of additional buffering. Moreover, the overhead decreases as utilization increases, or as the traffic becomes more bursty.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Indra Widjaja and Anwar I. Elwalid "Fast IP routing with VC-merge-capable ATM switches", Proc. SPIE 3233, Broadband Networking Technologies, (6 October 1997); https://doi.org/10.1117/12.290481
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KEYWORDS
Virtual colonoscopy

Switches

Asynchronous transfer mode

Switching

Internet

Associative arrays

Receivers

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