Two techniques for performing pixel level analog to digital conversion (ADC) are reviewed. The first is an over-sampling technique which uses a one bit first order (Sigma) (Delta) modulator for each 2 X 2 block of pixels to directly convert photocharge to bits. Each modulator is implemented using 17 transistors. The second technique is a Nyquist rate multi-channel-bit-serial (MCBS) ADC. The technique use successive comparisons to convert the pixel voltage to bits. Results obtained from implementations of these ADC techniques are presented. The techniques are compared based on size, charge handling capacity, FPN, noise sensitivity, data throughput, quantization, memory/processing, and power dissipation requirements for both visible an dIR imagers. From the comparison it appears that the (Sigma) (Delta) ADC is better suited to IR imagers, while the MCBS ADC is better suited to imagers in the visible range.

Several technologies have been developed in recent years to advance the state of the art of IR sensor systems including dual color affordable focal planes, on-focal plane array biologically inspired image and signal processing techniques and spectral sensing techniques. Pacific Advanced Technology (PAT) and the Air Force Research Lab Munitions Directorate have developed a system which incorporates the best of these capabilities into a single device. The 'NeuroSeek' device integrates these technologies into an IR focal plane array (FPA) which combines multicolor Midwave IR/Longwave IR radiometric response with on-focal plane 'smart' neuromorphic analog image processing. The readout and processing integrated circuit very large scale integration chip which was developed under this effort will be hybridized to a dual color detector array to produce the NeuroSeek FPA, which will have the capability to fuse multiple pixel-based sensor inputs directly on the focal plane. Great advantages are afforded by application of massively parallel processing algorithms to image data in the analog domain; the high speed and low power consumption of this device mimic operations performed in the human retina.

We have developed a high-resolution, superconducting analog- to-digital converter (ADC) based on phase modulation- demodulation architecture. The circuit is implemented in rapid single flux quantum electronics, using niobium technology. Extremely low on-chip power dissipation makes this ADC attractive for digital readout of cooled IR detectors. The output of the ADC is serially extracted from the chip to minimize the thermal load of input-output cables connecting the cold ADC to the room-temperature data acquisition system. The ADC performance can be enhanced by a multiple channel synchronize and a decimation filter. Designs of the various ADC circuits with increasing complexity and performance are discussed. Experimental results of 12-bit and 16-bit serial ADC circuits are also described. Recent developments in improving the performance of cryogenic laser diodes are discussed in relation to the possibility of optical readout of the ADC output. We also report the development of a compact packaging module for the ADC chip and the laser.

Design and operation of a low noise CMOS focal pa;ne readout circuit with ultra-high charge handling capacity is presented. Designed for high-background, VLWIR detector readout, each readout unit cell use an accurate dynamic current memory for automatic subtraction of the dark pedestal in current domain enabling measurement of small signals 85 dB below the dark level. The redout circuit operates with low-power dissipation, high linearity, and is capable of handling pedestal currents up to 300 nA. Measurements indicate an effective charge handling capacity of over 5 X 10⁹ charges/pixel with less than 10⁵ electrons of input referred noise.

A new readout method of coal pane array - correlated readout is presented for the first time. The interface circuit of this method is modeled as to charge and discharge the integration capacitor according to a control signal. Combined with an optical modulator, this readout method will be able to increase image's dynamic range and signal-to- noise ratio more effectively for strong background application. It will not only increase the output voltage swing but also attenuate noises that have lower frequency than the modulation frequency. Several interface circuits are designed and studied. SPICE simulation results show that correlated capacitive transimpedance amplifier may become a very promising correlated readout circuit. In order to study this new method experimentally by visible imager, a 16 by 16 silicon CMOS FPA demo chip has been designed, along with a test system. The application of this method on solar megnetrograph measurement is discussed.

Based on the application of the source follower per detector (SFD) input biasing technique, a new redout structure for the IR focal-plane-array (FPA), called the variable gain source follower per detector (VGSFD) is proposed and analyzed. The readout circuit of VGSFD of a unit cell of pyroelectric sensor under investigation, is composed of a source follower per detector circuit, high gain amplifier, and the reset switch. The VGSFD readout chip has been designed in 0.5 micrometers double-poly-double-metal n-well CMOS technology in various formats from 8 by 8 to 128 by 128. The experimental 8 by 8 VGSFD measurement results of the fabricated readout chip at room temperature have successfully verified both the readout function and performance. The high gain, low power, high sensitivity readout performances are achieved in a 50 by 50 micrometers ² pixel size.

The progress of the JPL in developing gallium arsenide junction field-effect transistors (GaAs JFETs) for application in RI readout electronics operating below 10 Kelvin is discussed. Results on GaAs JFETs fabricated using a highly isotropic HF-based etchant have been presented previously by our group. The isotropic etch reduced the typical input leakage current at 4K to less than 1 fA. These JFETs had a low frequency noise of just under 1 (mu) V/Hz^1/2 at 1 Hz at 4K, while dissipating less than 1 (mu) W of power. Building on this work, we have fabricated small-scale integrated circuits based on this GaAs JFET technology. In this paper we report on the fabrication of small-scale integrated circuit multiplexers and amplifiers. An 8 by 1 source-follower-per-detector multiplexer and a three-transistor differential pair have been fabricated and are fully functional at 4K. The input-referred noise and leakage current is consistent with that for the discrete devices. A systematic study of the device size dependence of the noise has been started, but as yet is inconclusive.

This paper describes a standardized high performance 320 by 256 readout integrated circuit for p-on-n detectors such as InSb, heterojunction HgCdTe, QWIP, and InGaAs. The array is intended to support a wide range of systems through flexibility and advanced modes of operation. The ISC9705 uses a flexible, programmable, multistage pipelined architecture to achieve a state-of-the-art ROIC suitable for applications ranging from hand-held IR viewers to high-speed industrial imaging systems. A simplified 'hands-off' default mode directly supports single output NTSSC or PAL operation. Using the programmable mode, the ISC9705 supports such advanced features as dynamic image transposition, dynamic windowing, multiple high-speed multiple output configurations, and signal 'skimming'. Both default and programmed modes support integrate-while-read and integrate- then-read snap shot operation, and variable gain.

The availability of submicron CMOS has enabled the development of shingle-chip IR cameras having performance capabilities and on-chip functions which were previously impossible. Sensor designers are, however, encoutering and overcoming several challanges including steadily decreasing operating voltage.

An active pixel sensor (APS) integrated in standard CMOS process technology is shown to be superior to an alternative passive pixel sensor (PPS). Further, the CMOS APS provides video sensitivity and SNR comparable to CCDs. Though the CMOS PPS has lower performance, it offers >50% optical fill factor without microlenses and can be produced at lower cost for applications not requiring broadcast quality SNR (>35 dB) under low light conditions (<20 lx). APS and PPS SNRs of 50 dB and 44 dB are reported at 200 lx using green filtering with ~80 nm bandpass.

This paper present a novel low cost, high performance readout integrated circuit (ROIC) for bolometer uncooled detector applications. The array is designed to offer better than 80mK NEdT using f/1.8 optics. The design incorporates advanced on-ROIC signal processing electronics that allows bolometer element non-uniformity control over a wide range of ROIC substrate temperatures. The small format array is ideally suited for high volume low-cost production applications.

At temperatures below 20K conventional MOS transistors continue to work, but excessive noise and current-voltage anomalies such as kink effect and hysteresis appear on their output characteristics because of carrier freeze-out in silicon. A cryogenic MOS transistor was proposed to prevent the anomalies. The paper describes the cryogenic transistor structure, its performance and the result of its application in a 64 by 1 CMOS multiplexer.

Temperature dependent mobility in the device simulation program has been used to check whether they are adequate to simulate device characteristics under low temperature operation. The study here shows that although the mobility models in the simulation program can be used to simulate room temperature device characteristics, care should be taken for the low temperature simulation. By substituting the extracted mobility table or the suitable mobility model into the simulation program, better simulation results can be obtained. To this point, we believe that there is still a need to develop a better and more concentrated and temperature dependent mobility model.